Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

11. CoreSight* Debug and Trace

CoreSight* systems provide all the infrastructure you require to debug, monitor, and optimize the performance of a complete HPS design. CoreSight* technology addresses the requirement for a multicore debug and trace solution with high bandwidth for whole systems beyond the processor core.

CoreSight* technology provides the following features:

  • Cross-trigger support between SoC subsystems
  • High data compression
  • Multi-source trace in a single stream
  • Standard programming models for standard tool support

The hard processor system (HPS) debug infrastructure provides visibility and control of the HPS modules, the Arm* Cortex®-A9 microprocessor unit (MPU) subsystem, and user logic implemented in the FPGA fabric. The debug system design incorporates Arm* CoreSight* components.

Details of the Arm* CoreSight* debug components can be viewed by clicking on the following related information links: