Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

10.5.1.5. L2 Cache Event Monitoring

The L2 cache supports the built‑in cache event monitoring signals shown in the table below. The L2 cache can count two of the events at any one time.

Table 67.  L2 Cache Events

Event

Description

CO

Eviction (cast out) of a line from the L2 cache.

DRHIT

Data read hit in the L2 cache.

DRREQ

Data read lookup to the L2 cache. Subsequently results in a hit or miss.

DWHIT

Data write hit in the L2 cache.

DWREQ

Data write lookup to the L2 cache. Subsequently results in a hit or miss.

DWTREQ

Data write lookup to the L2 cache with write‑through attribute. Subsequently results in a hit or miss.

EPFALLOC

Prefetch hint allocated into the L2 cache.

EPFHIT

Prefetch hint hits in the L2 cache.

EPFRCVDS0

Prefetch hint received by slave port S0.

EPFRCVDS1

Prefetch hint received by slave port S1.

IPFALLOC

Allocation of a prefetch generated by L2 cache controller into the L2 cache.

IRHIT

Instruction read hit in the L2 cache.

IRREQ

Instruction read lookup to the L2 cache. Subsequently results in a hit or miss.

SPNIDEN

Secure privileged non‑invasive debug enable.

SRCONFS0

Speculative read confirmed in slave port S0.

SRCONFS1

Speculative read confirmed in slave port S1.

SRRCVDS0

Speculative read received by slave port S0.

SRRCVDS1

Speculative read received by slave port S1.

WA

Allocation into the L2 cache caused by a write (with write‑allocate attribute) miss.

In addition, the L2 cache events can be captured and timestamped using dedicated debugging circuitry.