Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

10.1. Features of the Cortex-A9 MPU Subsystem

The Intel Cortex®-A9 MPU subsystem provides the following features:

  • Two Arm* Cortex®-A9 processors, each with the following support modules:
    • Arm* NEON* single instruction, multiple data (SIMD) coprocesoor
    • Memory Management Unit (MMU)
    • 32 KB instruction cache
    • 32 KB data cache
    • Private interval timer
    • Private watchdog timer
  • Interrupt controller
  • Global timer
  • Snoop control unit (SCU)
  • Accelerator Coherency Port (ACP)
  • Arm* L2 cache controller
  • TrustZone* system security extensions
  • Symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP) modes
  • Debugging modules
The Cortex®-A9 MPU incorporates the following core and L2 cache versions:
Table 56.   Cortex®-A9 MPU Module Versions

Feature

Version

Cortex®-A9 Core

r3p0

L2-310 Level 2 Cache Controller

r3p3