Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

A.4.5. Clock Select

The boot ROM reads the clock select values to determine what frequency has been selected for the CPU clock and any interface clock during boot.

The clock select (CSEL) pins are asserted to select the speed of the HPS boot interface. If the FPGA is used as the boot source, the CSEL pins are ignored. The CSEL values define the main PLL, l2_mp_clk and l4_sp_clk. Based on the clock source and clock select settings, boot ROM configures the main PLL and peripheral PLL parameters and the clock dividers for clocks derived from the PLLs.

Note: The terms CSEL and CLKSEL are used interchangeably in Intel® documentation to refer to clock select.
Note: At power-up or reset, when CSEL[1:0]=0x0 or BSEL[2:0] is configured to boot from FPGA, the HPS PLLs are in bypass mode. Thus, HPS user clocks exported to the FPGA fabric run at osc1_clk frequency.