Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

3.3.3.3. Peripheral Clock Group

The peripheral clock group consists of a PLL, dividers, and clock gating. The clocks in the peripheral clock group are derived from the peripheral PLL. The peripheral PLL can be programmed to be sourced from the HPS_CLK1 pin, the HPS_CLK2 pin, or the f2h_periph_ref_clk clock provided by the FPGA fabric.

The FPGA fabric must be configured with an image that provides the f2h_periph_ref_clk before selecting it as the clock source. If the FPGA must be reconfigured and f2h_periph_ref_clk is being used by modules in the HPS, an alternate clock source must be selected prior to reconfiguring the FPGA.

Clocks that always use the peripheral PLL output clocks as the clocks source are:

  • emac0_clk
  • emac1_clk
  • usb_mp_clk
  • spi_m_clk
  • gpio_db_clk
  • h2f_user1_clk

In addition, clocks that may use the peripheral PLL output clocks as the clock source are:

  • sdmmc_clk
  • nand_clk
  • qspi_clk
  • l4_mp_clk
  • l4_sp_clk

The counter outputs from the main PLL can have their frequency further divided by external dividers. Transitions to a different divide value occur on the fastest output clock, one clock cycle prior to the slowest clock’s rising edge. For example, the clock transitions on cycle 15 of the divide‑by‑16 divider for the main C2 output and cycle 3 of the divide‑by‑4 divider for the C1 output.

Table 11.  Peripheral PLL Output Assignments

PLL

Output Counter

Clock Name

Frequency

Phase Shift Control

Peripheral

C0

emac0_base_clk

Up to 250 MHz

No

C1

emac1_base_clk

Up to 250 MHz

No

C2

periph_qspi_base_clk

Up to 432 MHz

No

C3

periph_nand_sdmmc_base_clk

Up to 250 MHz for the NAND flash controller and up to 200 MHz for the SD/MMC controller

No

C4

periph_base_base_clk

Up to 240 MHz for the SPI masters and up to 200 MHz for the scan manager

No

C5

h2f_user1_base_clk

osc1_clk to 100 MHz

No

The following figure shows programmable post-PLL dividers and clock gating for the peripheral clock group. Clock gate blocks in the diagram indicate clocks that may be gated off under software control. Software is expected to gate these clocks off prior to changing any PLL or divider settings that might create incorrect behavior on these clocks.

Figure 7. Peripheral Clock Group Divide and Gating
Table 12.  Peripheral Clock Group Clocks

System Clock Name

Frequency

Divided From

Constraints and Notes

usb_mp_clk

Up to 200 MHz

Peripheral PLL C4

Clock for USB

spi_m_clk

Up to 240 MHz for the SPI masters and up to 200 MHz for the scan manager

Peripheral PLL C4

Clock for L4 SPI master bus and scan manager

emac0_clk

Up to 250 MHz

Peripheral PLL C0

EMAC0 clock. The 250 MHz clock is divided internally by the EMAC into the typical 125/25/2.5 MHz speeds for 1000/100/10 Mbps operation.

emac1_clk

Up to 250 MHz

Peripheral PLL C1

EMAC1 clock

The 250 MHz clock is divided internally by the EMAC into the typical 125/25/2.5 MHz speeds for 1000/100/10 Mbps operation.

l4_mp_clk

Up to 100 MHz

Main PLL C1 or peripheral PLL C4

Clock for L4 master peripheral bus

l4_sp_clk

Up to 100 MHz

Main PLL C1 or peripheral PLL C4

Clock for L4 slave peripheral bus

gpio_db_clk

Up to 1 MHz

Peripheral PLL C4

Used to debounce GPIO0, GPIO1, and GPIO2

h2f_user1_clock

Peripheral PLL C5

Peripheral PLL C5

Auxiliary user clock to the FPGA fabric