Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

A.5. Boot ROM Flow

On a cold reset, the HPS boot process starts when CPU0 is released from reset (for example, on a power up) and executes code in the internal boot ROM at the reset exception address. The boot ROM code brings the SoC out of reset and into a known state. After boot ROM code is exited, control passes to the next stage of the boot software, referred to as the preloader. The preloader can be customized and is typically stored external to the HPS in a nonvolatile flash-based memory or in on-chip RAM within the FPGA. Beyond that, another boot layer can be executed before loading the operating system software.

This section describes the software flow from reset until the boot ROM code passes software control to the preloader.

The following figure illustrates that the boot ROM code can perform a warm boot from on-chip RAM, a cold boot from the FPGA portion of the device, or a cold boot from flash memory.

Figure 148. BOOT ROM FLOW

After a reset, the boot ROM code determines which CPU it is executing on. If it is executing on CPU 1, then control is passed to CPU1 and the boot ROM execution is complete. This event only happens if the user code releases CPU1 without resetting the exception vectors.

If the boot ROM is executing on CPU0, it checks to see if an on-chip RAM boot is requested. An on-chip RAM boot can only occur on a warm reset. Warm boot from on-chip RAM has the highest priority to execute if the warmramgrp registers in the romcodegrp group in the system manager has been configured to support booting from on-chip RAM on a warm reset. If the enable register in the System Manager is set to 0xAE9EFEBC, then the boot ROM code attempts to boot from on-chip RAM on a warm reset and the boot ROM does not configure boot I/Os, pin-muxes or clocks. The datastart and length registers in System Manager allow you to program the offset of the beginning of code and the length of the region of on-chip RAM for CRC validation. If the length register is clear, then boot ROM does not perform a CRC calculation on the on-chip RAM.

If a valid preloader image cannot be found in the on-chip RAM, or the preloader in the on-chip RAM fails the CRC check, the boot ROM code attempts to load the last valid preloader image loaded from the flash memory, identified by the index field of the initial software last image loaded register (initswlastld) in the romcodegrp group in the system manager. If the image is invalid, boot ROM code attempts to load up to three subsequent images from flash memory. If a valid preloader image cannot be found in the on-chip RAM or flash memory, the boot ROM code checks the FPGA portion of the device for a fallback image.

If the warm RAM boot has failed or if a cold reset has occurred, then the boot ROM reads the BSEL value in the bootinfo register of the System Manager. If the FPGA is selected as the boot source, then the boot ROM code attempts to execute code at address 0xC0000000 across the HPS-to-FPGA bridge (offset 0x00000000 from bridge). No error conditions are generated if the FPGA does not initialize properly and the watchdog is not enabled for time-out. Instead, the boot ROM continues to wait until the FPGA is available.

If the BSEL bits indicate a boot from external flash, then the boot ROM code attempts to load an image from a flash device into the on-chip RAM, verify and execute it. If the BSEL is invalid or the boot ROM code cannot find a valid image in the flash, then the boot ROM code checks if there is a fallback image in the FPGA. If there is, then the boot ROM executes the fallback image. If there is no fallback image then the boot ROM performs a post-mortem dump of information into the on-chip RAM and awaits a reset.

Note: The acronyms BSEL and BOOTSEL are used interchangeably to define the boot select pins.