Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

29.1.2. Generating the HPS Simulation Model in Platform Designer (Standard)

The following steps outline how to generate the simulation model:

  1. In Platform Designer (Standard), click Generate HDL under the Generate menu.
  2. Choose between RTL and post–fit simulation
    For RTL simulation, perform the following steps:
    1. Set Create simulation model to Verilog.
    2. Click Generate.66
    For post–fit simulation, perform the following steps:
    1. Turn on the Create HDL design files for synthesis option.
    2. Turn on the Create block symbol file (.bsf) option.67 68
  3. Click Generate.
66 VHDL is supported for HPS simulation and it requires a mix language simulator. However, the BFMs always need to be in verilog. Custom components can be in VHDL.
67 A .bsf file is only needed for schematic entry.
68 This is not a requirement for simulation or implementation unless a schematic is used.