Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

10.3.15.3.1. Configuring AxCACHE[3:0] Sideband Signals for Coherent Accesses

The following list highlights how to correctly derive and apply the correct AxCACHE settings for coherent accesses.
  • The correct AxCACHE[3:0] setting is dependent on the MMU page table settings. However, for coherent accesses, AxCACHE[1] must be set to 0x1.
  • If an HPS peripheral uses the ACP for coherent master accesses, then the AxCACHE properties must be configured in the corresponding System Manager register for that peripheral and the ACP ID mapper must be configured for the appropriate AxUSER properties.
  • For FPGA masters, AxCACHE[3:0] is applied in the FPGA fabric and can be set for each access.