Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

24.3.1. Clocks

Table 211.  Timer Clock Characteristics

Timer

System Clock

Notes

OSC1 timer 0

osc1_clk

OSC1 timer 1

SP timer 0

l4_sp_clk

Timer must be disabled if clock frequency changes

SP timer 1

The timers above are labeled according to the clock it receives. OSC timers receive the oscillator clock osc1_clk and the SP timers receives the l4 slave peripheral clock l4_sp_clk .

SP timer 0 and SP timer 1 must be disabled before l4_sp_clk is changed to another frequency. You can then re-enable the timer once the clock frequency change takes effect. You cannot change the frequency of OSC1 timer 0 and OSC1 timer 1.