Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

27.1.1. General Interfaces

When enabled, the interfaces described in the following table become visible in the HPS component.

Table 212.  General Parameters

Parameter Name

Parameter Description

Interface Name

Enable MPU standby and event signals

Enables interfaces that perform the following functions:

  • Notify the FPGA fabric that the microprocessor unit (MPU) is in standby mode.
  • "16">Wake up an MPCore processor from a wait for event (WFE) state.

h2f_mpu_events

Enable general purpose signals

Enables a pair of 32-bit unidirectional general-purpose interfaces between the FPGA fabric and the FPGA manager in the HPS portion of the SoC device.

h2f_gp

Enable Debug APB* interface

Enables debug interface to the FPGA, allowing access to debug components in the HPS. For more information, refer to the CoreSight Debug and Trace chapter.

h2f_debug_apb

h2f_debug_apb_sideband

h2f_debug_apb_clock

h2f_debug_apb_reset

Enable System Trace Macrocell hardware events

Enables system trace macrocell (STM) hardware events, allowing logic inside the FPGA to insert messages into the trace stream. For more information, refer to the CoreSight Debug and Trace chapter.

f2h_stm_hw_events

Enable FPGA Cross Trigger interface

Enables the cross trigger interface (CTI), which allows trigger sources and sinks to interface with the embedded cross trigger (ECT). For more information, refer to the CoreSight Debug and Trace chapter.

h2f_cti

h2f_cti_clock

Enable FPGA Trace Port Interface Unit

Enables an interface between the trace port interface unit (TPIU) and logic in the FPGA. The TPIU is a bridge between on‑chip trace sources and a trace port. For more information, refer to the CoreSight Debug and Trace chapter.

h2f_tpiu

h2f_tpiu_clock_in

h2f_tpiu_clock

Enable boot from FPGA signals

Enables an input to the HPS indicating whether a preloader is available in the on-chip memory of the FPGA. This option also enables a separate input to the HPS indicating a fallback preloader is available in the FPGA memory. A fallback preloader is used when there is no valid preloader image found in flash memory. For more information, refer to Appendix A: Booting and Configuration.

f2h_boot_from_fpga

Enable HLGPI Interface

Enables a general purpose interface that is connected to the General Purpose I/O (GPIO) peripheral of HPS. This is an input-only interface with 14-bit width. This interface shares the I/O pins with the HPS DDR SDRAM controller.

hps_io (hps_io_gpio_inst_HLGPI[0..13])