SerialLite II IP Core User Guide

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ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

2.1. Parameterize the IP Core

The SerialLite II IP core parameter editor guides you through the setting of parameter values and selection of optional ports.
  1. Click Parameter Settings in the SerialLite II parameter editor. The Physical Layer page appears.
  2. Key in a data rate in megabits per second (Mbps). The SerialLite II IP core supports data rates of 622 to 6,375 Mbps per lane.
    Note: For Intel® Arria® 10 devices, the IP core supports higher than 6.375 Gbps per lane.
  3. Choose a Transfer size. The Transfer size determines the number of contiguous data columns. The Transfer size also determines the serialization/deserialization (SERDES) factor and internal data path width.
  4. Specify the Reference Clock Frequency. This option defines the frequency of the reference clock for the Arria II GX or Stratix IV internal transceiver. You can select any frequency supported by the transceiver.
    This option is not available in Arria® V, Cyclone® V, and Stratix® V configurations.
  5. Select a Port Type. You have three choices: Bidirectional, Transmitter only, and Receiver only.
    If you choose Transmitter only or Receiver only, the Self-Synchronized Link-Up parameter (LSM) is enabled by default.
  6. Turn on or off the Self-Synchronized Link-Up option. This parameter allows the receiver on the far end of the link to synchronize itself to incoming data streams, rather than on an exchange of status information with the transmitter.
    This feature is only for single lane applications.
  7. Under Transmitter Settings, select the number of lanes for the transmitter.
  8. Turn on or off the Scramble and Broadcast mode options.
  9. Under Receiver Settings, select the number of lanes for the receiver.
    Table 5.  Number of Transmit Lanes
    Self-Synchronized Link-Up Broadcast Number of Lanes
    On On 2 – 16
    On Off 1
    Off On 2 – 16
    Off Off 2 – 16
  10. Turn on or off the De-scramble option.
  11. Turn on or off the Enable frequency offset tolerance option.
  12. Click Configure Transceiver. Select the following parameters on the Configure Transceiver page to configure the ALTGX IP core for Arria® II GX and Stratix® IV devices.
    • For the transmitter, select the Voltage Output Differential (VOD) control setting value.
    • Under Pre-emphasis, select a value for Specify pre-emphasis control setting.
    • In the Bandwidth mode list, select high or low for the Tx PLL bandwidth.
    • Select a value for the Transmitter Buffer Power (VCCH).
    • Under Receiver Functionality, select a value for Specify equalizer control setting.
    • In the Bandwidth mode list, select high, medium or low for the Rx PLL bandwidth.
    • To reconfigure functionality settings, specify a Starting channel number.
    • Click Finish.
    The Configure Transceiver page is disabled when you select Arria® V, Cyclone® V, or Stratix® V as the target device family. To add a transceiver, you are required to instantiate the Custom PHY IP core.
    Note: If you want to use Intel® Arria® 10 devices, refer to the SerialLite II IP core release information in SerialLite II IP Core Overview for more details.
  13. Click Next to open the Link Layer page.
  14. Under Data Type, select Packets or Streaming.
  15. If you select Packets, select a packet type: Priority packets and data packets, Priority packets, or Data packets.
  16. If you select a packet type that includes priority packets, follow these substeps; otherwise, skip to Step 17.
    • Turn on or off the Retry-on-error option.
    • If you turned on Retry-on-error, specify a value for Timeout and Segment size.
    • Under Buffer Size, specify a value for Transmitter and Receiver.
    • Turn on or off the Enable flow control option.
    • If you turned on Enable flow control, specify the values for Pause quantum time, Threshold, and Refresh period.
    • If you selected Priority packets only, skip Step 17.
  17. If you selected a packet type that includes data packets, follow these substeps;
    • Turn on or off the Enable flow control option.
    • If you turned on Enable flow control, specify the values for Pause quantum time, Threshold, and Refresh period.
    • Under Buffer Size, specify a value for Transmitter and Receiver.
  18. If your transmitter or receiver requires cyclic redundancy code (CRC) checking, turn on the Enable CRC option for your chosen packet type and specify a value for CRC Type.
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