SerialLite II IP Core User Guide

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ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

1.1. General Description

The SerialLite II IP core is a simple, high-speed, low-latency, and low-resource point-to-point serial data communication link.
The SerialLite II IP core performs up to:
  • 3.75 Gbps in Arria® II GX devices
  • 5 Gbps in Cyclone® V devices
  • 6.375 Gbps in Arria® V, Stratix® IV, and Stratix® V devices
  • More than 6.375 Gbps in Intel® Arria® 10 devices

The SerialLite II IP core is highly configurable, and provides a wide range of functionality suited to moving data in many different environments.

The IP core provides a simple and lightweight way to move data from one point to another reliably at high speeds. It consists of a serial link of up to 16 bonded lanes, with logic to provide a number of basic and optional link support functions. The Atlantic interface is the primary access for delivering and receiving data.

The SerialLite II protocol specifies a link that is simple to build, uses as little logic as possible, and requires little work for a logic designer to implement. The SerialLite II MegaCore function uses all of the features available in the SerialLite II protocol. You can parameterize the IP core using the SerialLite II parameter editor.

A link built using the SerialLite II IP core operates at 622 Mbps to 6.375 Gbps per lane (or more for Intel® Arria® 10 devices). Link reliability is enhanced by the 8B10B encoding scheme and optional CRC capabilities. You can achieve further reductions in the bit-error rate by using the optional retry-on-error feature. Data rate and consumption mismatches can be accommodated using the optional flow-control feature to ensure that no data is lost.

Figure 1. SerialLite II IP Core High-Level Block DiagramThe SerialLite II IP core is divided into two main blocks: a protocol processing portion (data link layer) and a high-speed front end (physical layer).


You can use the SerialLite II IP core in the following applications:
  • Chip-to-chip connectivity
  • Board-to-board connectivity
  • Shelf-to-shelf connectivity
  • Backplane communication
  • Bridging applications
  • Streaming video applications
  • Imaging applications

The following diagrams show two examples of bridging applications.

Figure 2. Typical Application—Bridging Functions


Figure 3. Typical Application—Unidirectional Bridging Application


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