SerialLite II IP Core User Guide

Download PDF
ID 683179
Date 7/13/2021
Public
Document Table of Contents
Document Table of Contents x
1. SerialLite II IP Core Overview 2. SerialLite II IP Core Getting Started 3. SerialLite II IP Core Functional Description 4. SerialLite II IP Core Testbench 5. SerialLite II IP Core User Guide Archives 6. Document Revision History for the SerialLite II IP Core User Guide
1. SerialLite II IP Core Overview x
1.1. General Description 1.2. Performance and Resource Utilization
2. SerialLite II IP Core Getting Started x
2.1. Parameterize the IP Core 2.2. Set Up Simulation 2.3. Generate Files 2.4. Simulate the Design 2.5. Instantiate the IP Core 2.6. Compile and Program Specify Constraints 2.8. SerialLite II Parameter Settings
2.8. SerialLite II Parameter Settings x
2.8.1. Link Consistency 2.8.2. Data Rate 2.8.3. Reference Clock Frequency 2.8.4. Port Type 2.8.5. Self Synchronized Link Up 2.8.6. Scramble 2.8.7. Broadcast Mode 2.8.8. Lane Polarity and Order Reversal 2.8.9. Data Type 2.8.10. Packet Type 2.8.11. Flow Control Operation 2.8.12. Transmit/Receive FIFO Buffers 2.8.13. Data Integrity Protection: CRC 2.8.14. Transceiver Configuration 2.8.15. Error Handling 2.8.16. Optimizing the Implementation
2.8.10. Packet Type x
2.8.10.1. Retry-on-Error
2.8.11. Flow Control Operation x
2.8.11.1. Selecting the Proper Threshold Value 2.8.11.2. Selecting the Proper Pause Duration 2.8.11.3. Selecting the Proper Refresh Value 2.8.11.4. External Flow Control (When RX FIFO Size is 0)
2.8.14. Transceiver Configuration x
2.8.14.1. Voltage Output Differential (VOD) Control Settings 2.8.14.2. Pre-Emphasis Control Settings 2.8.14.3. Transmitter Buffer Power (VCCH) 2.8.14.4. Transceiver Reconfiguration Block 2.8.14.5. ALTGX Support Signals
2.8.16. Optimizing the Implementation x
2.8.16.1. Improving Performance 2.8.16.2. Minimizing Logic Utilization 2.8.16.3. Minimizing Memory Utilization
3. SerialLite II IP Core Functional Description x
3.1. Atlantic Interface 3.2. High-Speed Serial Interface 3.3. Clocks and Data Rates 3.4. Multiple Core Configuration 3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices 3.6. SerialLite II Signals 3.7. IP Core Verification
3.3. Clocks and Data Rates x
3.3.1. Aggregate Bandwidth 3.3.2. External Clock Modes 3.3.3. Internal Clocking Configurations 3.3.4. SerialLite II Deskew Support 3.3.5. SerialLite II Clocking Structure 3.3.6. SerialLite II Pin-Out Diagrams 3.3.7. Initialization and Restart
3.5. IP Core Configuration for Intel® Arria® 10, Arria® V, Cyclone® V, and Stratix® V Devices x
3.5.1. Design Consideration 3.5.2. Parameter Settings For SerialLite II and Custom PHY IP Cores 3.5.3. Extra Signals Between SerialLite II and Custom PHY IP Cores
4. SerialLite II IP Core Testbench x
4.1. Testbench Files 4.2. Testbench Specifications 4.3. Simulation Flow 4.4. Testbench Components
4.3. Simulation Flow x
4.3.1. Running a Simulation 4.3.2. Simulation Pass and Fail Conditions
4.3.2. Simulation Pass and Fail Conditions x
4.3.2.1. Value Change Dump (VCD) File Generation (For the Verilog HDL Testbench) 4.3.2.2. Testbench Time-Out 4.3.2.3. Special Simulation Configuration Settings 4.3.2.4. Atlantic Receiver Behavior
4.4. Testbench Components x
AGEN AMON 4.4.3. Status Monitors 4.4.4. Clock and Reset Generator 4.4.5. Custom PHY IP Core 4.4.6. Example Testbench – Verilog HDL
1. SerialLite II IP Core Overview
2. SerialLite II IP Core Getting Started
3. SerialLite II IP Core Functional Description
4. SerialLite II IP Core Testbench
5. SerialLite II IP Core User Guide Archives
6. Document Revision History for the SerialLite II IP Core User Guide

2.8.15. Error Handling

The SerialLite II IP core does error checking and has an interface to view local errors. The errors are categorized, and the effect of an error depends on the type of error that occurs.
The SerialLite II IP core has three error types:
  • Data error
  • Link error
  • Catastrophic error
Table 15.  Error SummaryThis table summarizes the causes and results of the SerialLite II error types.
Error Type Cause Action
Data
  • Invalid 8B/10B codes groups
  • Running disparity errors
  • Unsupported valid code groups
  • Link protocol violation
  • LMP with BIP error
  • CRC error
  • Unexpected channel number
  • Out of order packet
  • Out of order acknowledgment (if Retry-on-error is enabled)
Two possibilities:
  • If Retry-on-error is enabled and the packet is a priority packet, request retransmission.
  • Otherwise, mark the packet as bad and forward it to the user link layer.
Link
  • Eight consecutive {|TS1|} sequences received in all lanes simultaneously
  • Loss of character alignment
  • Loss of lane alignment
  • Loss of characters from underflow/overflow
  • Data error threshold exceeded
  • Retry-on-error timer expired three times
 Trigger link initialization
Catastrophic
  • LSM cannot reverse polarity
  • LSM cannot reorder lanes
 SerialLite II enters nonrecoverable state
Packets Marked Bad {EBP} marked packet Received packet is marked as bad through the rxrdp_err or rxhpp_err signals, and forwarded to the user link layer.
Error signals, such as txrdp_err and txhpp_err, are asserted by user logic.
  • When txrdp_err is asserted with txrdp_eop, the packet is marked with the end of bad packet {EBP} marker.
  • The txrdp_err signal is ignored when it is not asserted with txrdp_eop.
  • When the txhpp_err is asserted and the Retry-on-error feature is turned off, the packet is marked with the {EBP} marker.
  • When the txhpp_err is asserted and the Retry-on-error feature is turned on, the packet is not transmitted and is silently dropped.
Level Two Title