Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.7.56. SIGNALRACE_RULE_RESET_RACE

Direct Design Assistant to detect synchronous port and asynchronous port of same register driven by same signal source

Type

Boolean

Device Support

  • Cyclone
  • E
  • MAX II
  • MAX V
  • Mercury
  • Stratix
  • Stratix GX

Notes

None

Syntax


		set_global_assignment -name SIGNALRACE_RULE_RESET_RACE <value>