Altera® Quartus® Prime Standard Edition Settings File Reference Manual

ID 683084
Date 5/08/2017
Public
Document Table of Contents

1.7.10. CLK_RULE_INPINS_CLKNET

Direct Design Assistant to check illegal input pins connected to clock net used on the design.

Type

Boolean

Device Support

  • Cyclone
  • E
  • MAX II
  • MAX V
  • Mercury
  • Stratix
  • Stratix GX

Notes

None

Syntax


		set_global_assignment -name CLK_RULE_INPINS_CLKNET <value>