Altera® Quartus® Prime Standard Edition Settings File Reference Manual

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ID 683084
Date 5/08/2017
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Document Table of Contents
Document Table of Contents x
1. Altera® Quartus® Prime Standard Edition Settings File Reference Manual
1. Altera® Quartus® Prime Standard Edition Settings File Reference Manual x
1.1. Advanced I/O Timing Assignments 1.2. Analysis & Synthesis Assignments 1.3. Assembler Assignments 1.4. Assignment Group Assignments 1.5. Classic Timing Assignments 1.6. Compiler Assignments 1.7. Design Assistant Assignments 1.8. EDA Netlist Writer Assignments 1.9. Equivalence Checker Assignments 1.10. Fitter Assignments 1.11. Incremental Compilation Assignments 1.12. LogicLock Region Assignments 1.13. Migration Assignments 1.14. Netlist Viewer Assignments 1.15. Pin & Location Assignments 1.16. Power Estimation Assignments 1.17. Programmer Assignments 1.18. Project-Wide Assignments 1.19. SignalProbe Assignments 1.20. SignalTap II Assignments 1.21. Simulator Assignments
1.1. Advanced I/O Timing Assignments x
1.1.1. BOARD_MODEL_EBD_FAR_END 1.1.2. BOARD_MODEL_EBD_FILE_NAME 1.1.3. BOARD_MODEL_EBD_SIGNAL_NAME 1.1.4. BOARD_MODEL_FAR_C 1.1.5. BOARD_MODEL_FAR_DIFFERENTIAL_R 1.1.6. BOARD_MODEL_FAR_PULLDOWN_R 1.1.7. BOARD_MODEL_FAR_PULLUP_R 1.1.8. BOARD_MODEL_FAR_SERIES_R 1.1.9. BOARD_MODEL_NEAR_C 1.1.10. BOARD_MODEL_NEAR_DIFFERENTIAL_R 1.1.11. BOARD_MODEL_NEAR_PULLDOWN_R 1.1.12. BOARD_MODEL_NEAR_PULLUP_R 1.1.13. BOARD_MODEL_NEAR_SERIES_R 1.1.14. BOARD_MODEL_NEAR_TLINE_C_PER_LENGTH 1.1.15. BOARD_MODEL_NEAR_TLINE_LENGTH 1.1.16. BOARD_MODEL_NEAR_TLINE_L_PER_LENGTH 1.1.17. BOARD_MODEL_TERMINATION_V 1.1.18. BOARD_MODEL_TLINE_C_PER_LENGTH 1.1.19. BOARD_MODEL_TLINE_LENGTH 1.1.20. BOARD_MODEL_TLINE_L_PER_LENGTH 1.1.21. ENABLE_ADVANCED_IO_TIMING 1.1.22. OUTPUT_IO_TIMING_ENDPOINT 1.1.23. OUTPUT_IO_TIMING_FAR_END_VMEAS 1.1.24. OUTPUT_IO_TIMING_NEAR_END_VMEAS 1.1.25. PCB_LAYER 1.1.26. PCB_LAYERS 1.1.27. PCB_LAYER_THICKNESS 1.1.28. SYNCHRONOUS_GROUP
1.2. Analysis & Synthesis Assignments x
1.2.1. ADV_NETLIST_OPT_ALLOWED 1.2.2. ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION 1.2.3. ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION 1.2.4. ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION 1.2.5. ALLOW_CHILD_PARTITIONS 1.2.6. ALLOW_POWER_UP_DONT_CARE 1.2.7. ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES 1.2.8. ALLOW_SYNCH_CTRL_USAGE 1.2.9. ALLOW_XOR_GATE_USAGE 1.2.10. ALTERA_A10_IOPLL_BOOTSTRAP 1.2.11. AUTO_CARRY_CHAINS 1.2.12. AUTO_CASCADE_CHAINS 1.2.13. AUTO_CLOCK_ENABLE_RECOGNITION 1.2.14. AUTO_DSP_RECOGNITION 1.2.15. AUTO_ENABLE_SMART_COMPILE 1.2.16. AUTO_GLOBAL_CLOCK_MAX 1.2.17. AUTO_GLOBAL_OE_MAX 1.2.18. AUTO_IMPLEMENT_IN_ROM 1.2.19. AUTO_LCELL_INSERTION 1.2.20. AUTO_OPEN_DRAIN_PINS 1.2.21. AUTO_PARALLEL_EXPANDERS 1.2.22. AUTO_PARALLEL_SYNTHESIS 1.2.23. AUTO_RAM_BLOCK_BALANCING 1.2.24. AUTO_RAM_RECOGNITION 1.2.25. AUTO_RAM_TO_LCELL_CONVERSION 1.2.26. AUTO_RESOURCE_SHARING 1.2.27. AUTO_ROM_RECOGNITION 1.2.28. AUTO_SHIFT_REGISTER_RECOGNITION 1.2.29. BLOCK_DESIGN_NAMING 1.2.30. BOARD 1.2.31. CARRY_CHAIN_LENGTH 1.2.32. CASCADE_CHAIN_LENGTH 1.2.33. CLKLOCKX1_INPUT_FREQ 1.2.34. CYCLONEII_OPTIMIZATION_TECHNIQUE 1.2.35. CYCLONE_OPTIMIZATION_TECHNIQUE 1.2.36. DEVICE_FILTER_PACKAGE 1.2.37. DEVICE_FILTER_PIN_COUNT 1.2.38. DEVICE_FILTER_SPEED_GRADE 1.2.39. DEVICE_FILTER_VOLTAGE 1.2.40. DISABLE_DSP_NEGATE_INFERENCING 1.2.41. DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES 1.2.42. DONT_MERGE_REGISTER 1.2.43. DQS_DELAY 1.2.44. DQS_FREQUENCY 1.2.45. DQS_SHIFT 1.2.46. DQS_SYSTEM_CLOCK 1.2.47. DSE_SYNTH_EXTRA_EFFORT_MODE 1.2.48. DSP_BLOCK_BALANCING 1.2.49. EDA_DESIGN_ENTRY_SYNTHESIS_TOOL 1.2.50. EDA_INPUT_DATA_FORMAT 1.2.51. EDA_INPUT_GND_NAME 1.2.52. EDA_INPUT_VCC_NAME 1.2.53. EDA_LMF_FILE 1.2.54. EDA_RUN_TOOL_AUTOMATICALLY 1.2.55. EDA_SHOW_LMF_MAPPING_MESSAGES 1.2.56. EDA_VHDL_LIBRARY 1.2.57. ENABLE_IP_DEBUG 1.2.58. ENABLE_M512 1.2.59. ENABLE_STATE_MACHINE_INFERENCE 1.2.60. EXTRACT_VERILOG_STATE_MACHINES 1.2.61. EXTRACT_VHDL_STATE_MACHINES 1.2.62. FAMILY 1.2.63. FORCE_SYNCH_CLEAR 1.2.64. HDL_INITIAL_FANOUT_LIMIT 1.2.65. HDL_MESSAGE_LEVEL 1.2.66. HDL_MESSAGE_OFF 1.2.67. HDL_MESSAGE_ON 1.2.68. HPS_PARTITION 1.2.69. IGNORE_CARRY_BUFFERS 1.2.70. IGNORE_CASCADE_BUFFERS 1.2.71. IGNORE_GLOBAL_BUFFERS 1.2.72. IGNORE_LCELL_BUFFERS 1.2.73. IGNORE_MAX_FANOUT_ASSIGNMENTS 1.2.74. IGNORE_ROW_GLOBAL_BUFFERS 1.2.75. IGNORE_SOFT_BUFFERS 1.2.76. IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF 1.2.77. IGNORE_VERILOG_INITIAL_CONSTRUCTS Type Device Support Notes Syntax Default Value Example 1.2.78. IMPLEMENT_AS_CLOCK_ENABLE 1.2.79. IMPLEMENT_AS_OUTPUT_OF_LOGIC_CELL 1.2.80. INFER_RAMS_FROM_RAW_LOGIC 1.2.81. IP_SEARCH_PATHS 1.2.82. LCELL_INSERTION 1.2.83. LIMIT_AHDL_INTEGERS_TO_32_BITS 1.2.84. MAX7000_FANIN_PER_CELL 1.2.85. MAX7000_IGNORE_LCELL_BUFFERS 1.2.86. MAX7000_IGNORE_SOFT_BUFFERS 1.2.87. MAX7000_OPTIMIZATION_TECHNIQUE 1.2.88. MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 1.2.89. MAXII_OPTIMIZATION_TECHNIQUE 1.2.90. MAX_AUTO_GLOBAL_REGISTER_CONTROLS 1.2.91. MAX_BALANCING_DSP_BLOCKS 1.2.92. MAX_FANOUT 1.2.93. MAX_LABS 1.2.94. MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS 1.2.95. MAX_RAM_BLOCKS_M4K 1.2.96. MAX_RAM_BLOCKS_M512 1.2.97. MAX_RAM_BLOCKS_MRAM 1.2.98. MERCURY_CARRY_CHAIN_LENGTH 1.2.99. MERCURY_OPTIMIZATION_TECHNIQUE 1.2.100. MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE 1.2.101. MUX_RESTRUCTURE 1.2.102. NOT_GATE_PUSH_BACK 1.2.103. NUMBER_OF_INVERTED_REGISTERS_REPORTED 1.2.104. NUMBER_OF_PROTECTED_REGISTERS_REPORTED 1.2.105. NUMBER_OF_REMOVED_REGISTERS_REPORTED 1.2.106. NUMBER_OF_SWEPT_NODES_REPORTED 1.2.107. NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 1.2.108. OCP_HW_EVAL 1.2.109. OPTIMIZATION_TECHNIQUE 1.2.110. OPTIMIZE_POWER_DURING_SYNTHESIS 1.2.111. PARALLEL_EXPANDER_CHAIN_LENGTH 1.2.112. PARALLEL_SYNTHESIS 1.2.113. PARAMETER 1.2.114. POWER_UP_LEVEL 1.2.115. PRESERVE_FANOUT_FREE_NODE 1.2.116. PRESERVE_REGISTER 1.2.117. PRE_MAPPING_RESYNTHESIS 1.2.118. PRPOF_ID 1.2.119. RBCGEN_CRITICAL_WARNING_TO_ERROR 1.2.120. REMOVE_DUPLICATE_REGISTERS 1.2.121. REMOVE_REDUNDANT_LOGIC_CELLS 1.2.122. REPORT_CONNECTIVITY_CHECKS 1.2.123. REPORT_PARAMETER_SETTINGS 1.2.124. REPORT_PARAMETER_SETTINGS_PRO 1.2.125. REPORT_SOURCE_ASSIGNMENTS 1.2.126. REPORT_SOURCE_ASSIGNMENTS_PRO 1.2.127. RESYNTHESIS_OPTIMIZATION_EFFORT 1.2.128. RESYNTHESIS_PHYSICAL_SYNTHESIS 1.2.129. RESYNTHESIS_RETIMING 1.2.130. SAFE_STATE_MACHINE 1.2.131. SAVE_DISK_SPACE 1.2.132. SEARCH_PATH 1.2.133. SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL 1.2.134. SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES 1.2.135. STATE_MACHINE_PROCESSING 1.2.136. STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT 1.2.137. STRATIXII_CARRY_CHAIN_LENGTH 1.2.138. STRATIXII_OPTIMIZATION_TECHNIQUE 1.2.139. STRATIX_CARRY_CHAIN_LENGTH 1.2.140. STRATIX_OPTIMIZATION_TECHNIQUE 1.2.141. STRICT_RAM_RECOGNITION 1.2.142. SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 1.2.143. SYNTHESIS_EFFORT 1.2.144. SYNTHESIS_KEEP_SYNCH_CLEAR_PRESET_BEHAVIOR_IN_UNMAPPER 1.2.145. SYNTH_CLOCK_MUX_PROTECTION 1.2.146. SYNTH_GATED_CLOCK_CONVERSION 1.2.147. SYNTH_MESSAGE_LEVEL 1.2.148. SYNTH_PROTECT_SDC_CONSTRAINT 1.2.149. SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM 1.2.150. SYNTH_TIMING_DRIVEN_SYNTHESIS 1.2.151. TOP_LEVEL_ENTITY 1.2.152. TRUE_WYSIWYG_FLOW 1.2.153. USER_LIBRARIES 1.2.154. USE_GENERATED_PHYSICAL_CONSTRAINTS 1.2.155. USE_HIGH_SPEED_ADDER 1.2.156. USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING 1.2.157. VERILOG_CONSTANT_LOOP_LIMIT 1.2.158. VERILOG_INPUT_VERSION 1.2.159. VERILOG_LMF_FILE 1.2.160. VERILOG_MACRO 1.2.161. VERILOG_NON_CONSTANT_LOOP_LIMIT 1.2.162. VERILOG_SHOW_LMF_MAPPING_MESSAGES 1.2.163. VHDL_INPUT_LIBRARY 1.2.164. VHDL_INPUT_VERSION 1.2.165. VHDL_LMF_FILE 1.2.166. VHDL_SHOW_LMF_MAPPING_MESSAGES
1.3. Assembler Assignments x
1.3.1. ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE 1.3.2. AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE 1.3.3. AUTO_RESTART_CONFIGURATION 1.3.4. CLOCK_SOURCE 1.3.5. COMPRESSION_MODE 1.3.6. CONFIGURATION_CLOCK_DIVISOR 1.3.7. CONFIGURATION_CLOCK_FREQUENCY 1.3.8. CYCLONEIII_CONFIGURATION_DEVICE 1.3.9. CYCLONEII_M4K_COMPATIBILITY 1.3.10. CYCLONE_CONFIGURATION_DEVICE 1.3.11. DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE 1.3.12. ENABLE_ADV_SEU_DETECTION 1.3.13. ENABLE_AUTONOMOUS_PCIE_HIP 1.3.14. ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE 1.3.15. ENABLE_OCT_DONE 1.3.16. ENABLE_SPI_MODE_CHECK 1.3.17. EN_SPI_IO_WEAK_PULLUP 1.3.18. EN_USER_IO_WEAK_PULLUP 1.3.19. EPROM_USE_CHECKSUM_AS_USERCODE 1.3.20. EXTERNAL_FLASH_FALLBACK_ADDRESS 1.3.21. FALLBACK_TO_EXTERNAL_FLASH 1.3.22. FORCE_SSMCLK_TO_ISMCLK 1.3.23. GENERATE_HEX_FILE 1.3.24. GENERATE_PMSF_FILES 1.3.25. GENERATE_RBF_FILE 1.3.26. GENERATE_TTF_FILE 1.3.27. HARDCOPYII_POWER_ON_EXTRA_DELAY 1.3.28. HEXOUT_FILE_COUNT_DIRECTION 1.3.29. HEXOUT_FILE_START_ADDRESS 1.3.30. MAX7000S_JTAG_USER_CODE 1.3.31. MAX7000_JTAG_USER_CODE 1.3.32. MAX7000_USE_CHECKSUM_AS_USERCODE 1.3.33. MERCURY_CONFIGURATION_DEVICE 1.3.34. MERCURY_CONFIG_DEVICE_JTAG_USER_CODE 1.3.35. MERCURY_JTAG_USER_CODE 1.3.36. ON_CHIP_BITSTREAM_DECOMPRESSION 1.3.37. POF_VERIFY_PROTECT 1.3.38. POR_SCHEME 1.3.39. PR_BASE_MSF 1.3.40. PR_BASE_SOF 1.3.41. PR_SKIP_BASE_CHECK 1.3.42. PWRMGT_VOLTAGE_OUTPUT_FORMAT 1.3.43. RELEASE_CLEARS_BEFORE_TRI_STATES 1.3.44. RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND 1.3.45. SECURITY_BIT 1.3.46. STRATIXII_CONFIGURATION_DEVICE 1.3.47. STRATIXII_MRAM_COMPATIBILITY 1.3.48. STRATIX_CONFIGURATION_DEVICE 1.3.49. STRATIX_CONFIG_DEVICE_JTAG_USER_CODE 1.3.50. STRATIX_JTAG_USER_CODE 1.3.51. USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT 1.3.52. USE_CHECKSUM_AS_USERCODE 1.3.53. USE_CONFIGURATION_DEVICE
1.4. Assignment Group Assignments x
1.4.1. ASSIGNMENT_GROUP_EXCEPTION 1.4.2. ASSIGNMENT_GROUP_MEMBER
1.5. Classic Timing Assignments x
1.5.1. ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS 1.5.2. CUT_OFF_IO_PIN_FEEDBACK 1.5.3. CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS 1.5.4. CUT_OFF_READ_DURING_WRITE_PATHS 1.5.5. DEFAULT_HOLD_MULTICYCLE 1.5.6. DO_COMBINED_ANALYSIS 1.5.7. EMIF_SOC_PHYCLK_ADVANCE_MODELING 1.5.8. ENABLE_HPS_INTERNAL_TIMING 1.5.9. INPUT_TRANSITION_TIME 1.5.10. LVDS_FIXED_CLOCK_DATA_PHASE 1.5.11. MAX_CORE_JUNCTION_TEMP 1.5.12. MIN_CORE_JUNCTION_TEMP 1.5.13. NOMINAL_CORE_SUPPLY_VOLTAGE 1.5.14. PACKAGE_SKEW_COMPENSATION 1.5.15. PLL_EXTERNAL_FEEDBACK_BOARD_DELAY 1.5.16. TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT 1.5.17. TIMEQUEST_DO_CCPP_REMOVAL 1.5.18. TIMEQUEST_DO_REPORT_TIMING 1.5.19. TIMEQUEST_MULTICORNER_ANALYSIS 1.5.20. TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 1.5.21. TIMEQUEST_REPORT_SCRIPT 1.5.22. TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS 1.5.23. TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS 1.5.24. USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN
1.6. Compiler Assignments x
1.6.1. ALLOW_REGISTER_DUPLICATION 1.6.2. ALLOW_REGISTER_MERGING 1.6.3. OPTIMIZATION_MODE 1.6.4. TIMEQUEST_SPECTRA_Q
1.7. Design Assistant Assignments x
1.7.1. ACLK_CAT 1.7.2. ACLK_RULE_IMSZER_ADOMAIN 1.7.3. ACLK_RULE_NO_SZER_ACLK_DOMAIN 1.7.4. ACLK_RULE_SZER_BTW_ACLK_DOMAIN 1.7.5. CLK_CAT 1.7.6. CLK_RULE_CLKNET_CLKSPINES 1.7.7. CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 1.7.8. CLK_RULE_COMB_CLOCK 1.7.9. CLK_RULE_GATED_CLK_FANOUT 1.7.10. CLK_RULE_INPINS_CLKNET 1.7.11. CLK_RULE_INV_CLOCK 1.7.12. CLK_RULE_MIX_EDGES 1.7.13. DA_CUSTOM_RULE_FILE 1.7.14. DISABLE_DA_GX_RULE 1.7.15. DISABLE_DA_RULE 1.7.16. DRC_DEADLOCK_STATE_LIMIT 1.7.17. DRC_DETAIL_MESSAGE_LIMIT 1.7.18. DRC_FANOUT_EXCEEDING 1.7.19. DRC_GATED_CLOCK_FEED 1.7.20. DRC_REPORT_FANOUT_EXCEEDING 1.7.21. DRC_REPORT_TOP_FANOUT 1.7.22. DRC_TOP_FANOUT 1.7.23. DRC_VIOLATION_MESSAGE_LIMIT 1.7.24. ENABLE_DA_RULE 1.7.25. ENABLE_DRC_SETTINGS 1.7.26. FSM_CAT 1.7.27. FSM_RULE_DEADLOCK_STATE 1.7.28. FSM_RULE_NO_RESET_STATE 1.7.29. FSM_RULE_NO_SZER_ACLK_DOMAIN 1.7.30. FSM_RULE_UNREACHABLE_STATE 1.7.31. FSM_RULE_UNUSED_TRANSITION 1.7.32. HARDCOPY_FLOW_AUTOMATION 1.7.33. HARDCOPY_NEW_PROJECT_PATH 1.7.34. HCPY_CAT 1.7.35. HCPY_PLL_MULTIPLE_CLK_NETWORK_TYPES 1.7.36. HCPY_VREF_PINS 1.7.37. NONSYNCHSTRUCT_CAT 1.7.38. NONSYNCHSTRUCT_RULE_ASYN_RAM 1.7.39. NONSYNCHSTRUCT_RULE_COMBLOOP 1.7.40. NONSYNCHSTRUCT_RULE_COMB_DRIVES_RAM_WE 1.7.41. NONSYNCHSTRUCT_RULE_DELAY_CHAIN 1.7.42. NONSYNCHSTRUCT_RULE_ILLEGAL_PULSE_GEN 1.7.43. NONSYNCHSTRUCT_RULE_LATCH_UNIDENTIFIED 1.7.44. NONSYNCHSTRUCT_RULE_MULTI_VIBRATOR 1.7.45. NONSYNCHSTRUCT_RULE_REG_LOOP 1.7.46. NONSYNCHSTRUCT_RULE_RIPPLE_CLK 1.7.47. NONSYNCHSTRUCT_RULE_SRLATCH 1.7.48. RESET_CAT 1.7.49. RESET_RULE_COMB_ASYNCH_RESET 1.7.50. RESET_RULE_IMSYNCH_ASYNCH_DOMAIN 1.7.51. RESET_RULE_IMSYNCH_EXRESET 1.7.52. RESET_RULE_UNSYNCH_ASYNCH_DOMAIN 1.7.53. RESET_RULE_UNSYNCH_EXRESET 1.7.54. SIGNALRACE_CAT 1.7.55. SIGNALRACE_RULE_CLK_PORT_RACE 1.7.56. SIGNALRACE_RULE_RESET_RACE 1.7.57. SIGNALRACE_RULE_SECOND_SIGNAL_RACE 1.7.58. SIGNALRACE_RULE_TRISTATE 1.7.59. TIMING_CAT
1.8. EDA Netlist Writer Assignments x
1.8.1. EDA_BOARD_BOUNDARY_SCAN_OPERATION 1.8.2. EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL 1.8.3. EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL 1.8.4. EDA_BOARD_DESIGN_SYMBOL_TOOL 1.8.5. EDA_BOARD_DESIGN_TIMING_TOOL 1.8.6. EDA_BOARD_DESIGN_TOOL 1.8.7. EDA_DESIGN_EXTRA_ALTERA_SIM_LIB 1.8.8. EDA_DESIGN_INSTANCE_NAME 1.8.9. EDA_ENABLE_GLITCH_FILTERING 1.8.10. EDA_ENABLE_IPUTF_MODE 1.8.11. EDA_EXTRA_ELAB_OPTION 1.8.12. EDA_FLATTEN_BUSES 1.8.13. EDA_FORMAL_VERIFICATION_ALLOW_RETIMING 1.8.14. EDA_FORMAL_VERIFICATION_TOOL 1.8.15. EDA_FV_HIERARCHY 1.8.16. EDA_GENERATE_FUNCTIONAL_NETLIST 1.8.17. EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT 1.8.18. EDA_GENERATE_POWER_INPUT_FILE 1.8.19. EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT 1.8.20. EDA_GENERATE_TIMING_CLOSURE_DATA 1.8.21. EDA_IBIS_EXTENDED_MODEL_SELECTOR 1.8.22. EDA_IBIS_MODEL_SELECTOR 1.8.23. EDA_IBIS_MUTUAL_COUPLING 1.8.24. EDA_IBIS_SPECIFICATION_VERSION 1.8.25. EDA_IPFS_FILE 1.8.26. EDA_LAUNCH_CMD_LINE_TOOL 1.8.27. EDA_MAINTAIN_DESIGN_HIERARCHY 1.8.28. EDA_MAP_ILLEGAL_CHARACTERS 1.8.29. EDA_NATIVELINK_GENERATE_SCRIPT_ONLY 1.8.30. EDA_NATIVELINK_PORTABLE_FILE_PATHS 1.8.31. EDA_NATIVELINK_SIMULATION_SETUP_SCRIPT 1.8.32. EDA_NATIVELINK_SIMULATION_TEST_BENCH 1.8.33. EDA_NETLIST_WRITER_OUTPUT_DIR 1.8.34. EDA_RESYNTHESIS_TOOL 1.8.35. EDA_RTL_SIMULATION_RUN_SCRIPT 1.8.36. EDA_RTL_SIM_MODE 1.8.37. EDA_RTL_TEST_BENCH_FILE_NAME 1.8.38. EDA_RTL_TEST_BENCH_NAME 1.8.39. EDA_RTL_TEST_BENCH_RUN_FOR 1.8.40. EDA_SDC_FILE_NAME 1.8.41. EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED 1.8.42. EDA_SIMULATION_RUN_SCRIPT 1.8.43. EDA_SIMULATION_TOOL 1.8.44. EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE 1.8.45. EDA_SIMULATION_VCD_OUTPUT_TCL_FILE 1.8.46. EDA_SIMULATION_VCD_OUTPUT_TCL_FILE_NAME 1.8.47. EDA_TEST_BENCH_DESIGN_INSTANCE_NAME 1.8.48. EDA_TEST_BENCH_ENABLE_STATUS 1.8.49. EDA_TEST_BENCH_ENTITY_MODULE_NAME 1.8.50. EDA_TEST_BENCH_EXTRA_ALTERA_SIM_LIB 1.8.51. EDA_TEST_BENCH_FILE 1.8.52. EDA_TEST_BENCH_FILE_NAME 1.8.53. EDA_TEST_BENCH_GATE_LEVEL_NETLIST_LIBRARY 1.8.54. EDA_TEST_BENCH_MODULE_NAME 1.8.55. EDA_TEST_BENCH_NAME 1.8.56. EDA_TEST_BENCH_RUN_FOR 1.8.57. EDA_TEST_BENCH_RUN_SIM_FOR 1.8.58. EDA_TIME_SCALE 1.8.59. EDA_TIMING_ANALYSIS_TOOL 1.8.60. EDA_TRUNCATE_LONG_HIERARCHY_PATHS 1.8.61. EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY 1.8.62. EDA_VHDL_ARCH_NAME 1.8.63. EDA_WAIT_FOR_GUI_TOOL_COMPLETION 1.8.64. EDA_WRITER_DONT_WRITE_TOP_ENTITY 1.8.65. EDA_WRITE_DEVICE_CONTROL_PORTS 1.8.66. EDA_WRITE_NODES_FOR_POWER_ESTIMATION
1.9. Equivalence Checker Assignments x
1.9.1. EQC_AUTO_BREAK_CONE 1.9.2. EQC_AUTO_COMP_LOOP_CUT 1.9.3. EQC_AUTO_INVERSION 1.9.4. EQC_AUTO_PORTSWAP 1.9.5. EQC_AUTO_TERMINATE 1.9.6. EQC_BBOX_MERGE 1.9.7. EQC_CONSTANT_DFF_DETECTION 1.9.8. EQC_DETECT_DONT_CARES 1.9.9. EQC_DFF_SS_EMULATION 1.9.10. EQC_DUPLICATE_DFF_DETECTION 1.9.11. EQC_LVDS_MERGE 1.9.12. EQC_MAC_REGISTER_UNPACK 1.9.13. EQC_PARAMETER_CHECK 1.9.14. EQC_POWER_UP_COMPARE 1.9.15. EQC_RAM_REGISTER_UNPACK 1.9.16. EQC_RAM_UNMERGING 1.9.17. EQC_RENAMING_RULES 1.9.18. EQC_RENAMING_RULES_LIST 1.9.19. EQC_SET_PARTITION_BB_TO_VCC_GND 1.9.20. EQC_SHOW_ALL_MAPPED_POINTS 1.9.21. EQC_STRUCTURE_MATCHING 1.9.22. EQC_SUB_CONE_REPORT
1.10. Fitter Assignments x
1.10.1. ACTIVE_SERIAL_CLOCK 1.10.2. ADCE_ENABLED 1.10.3. ADVANCED_PHYSICAL_OPTIMIZATION 1.10.4. ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER 1.10.5. ALM_REGISTER_PACKING_EFFORT 1.10.6. ALWAYS_ENABLE_INPUT_BUFFERS 1.10.7. ASYNC_PIPELINE_DISABLE_DESTINATION_CHECK 1.10.8. ASYNC_PIPELINE_REG_REACH 1.10.9. AUTO_C3_M9K_BIT_SKIP 1.10.10. AUTO_DELAY_CHAINS 1.10.11. AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS 1.10.12. AUTO_GLOBAL_CLOCK 1.10.13. AUTO_GLOBAL_MEMORY_CONTROLS 1.10.14. AUTO_GLOBAL_OE 1.10.15. AUTO_GLOBAL_REGISTER_CONTROLS 1.10.16. AUTO_MERGE_PLLS 1.10.17. AUTO_PACKED_REGISTERS_MAX 1.10.18. AUTO_RESERVE_CLKUSR_FOR_CALIBRATION 1.10.19. AUTO_TURBO_BIT 1.10.20. BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE 1.10.21. BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES 1.10.22. BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS 1.10.23. BLOCK_RAM_TO_MLAB_CELL_CONVERSION 1.10.24. C3_M9K_BIT_SKIP 1.10.25. CARRY_OUT_PINS_LCELL_INSERT 1.10.26. CDR_BANDWIDTH_PRESET 1.10.27. CKN_CK_PAIR 1.10.28. CLAMPING_DIODE 1.10.29. CLOCK_ENABLE_ROUTING 1.10.30. CLOCK_REGION 1.10.31. CLOCK_TO_OUTPUT_DELAY 1.10.32. CONFIGURATION_VCCIO_LEVEL 1.10.33. CONVERT_PR_WARNINGS_TO_ERRORS 1.10.34. CRC_ERROR_CHECKING 1.10.35. CRC_ERROR_OPEN_DRAIN 1.10.36. CURRENT_STRENGTH_NEW 1.10.37. CVP_CONFDONE_OPEN_DRAIN 1.10.38. CVP_MODE 1.10.39. CYCLONEIII_CONFIGURATION_SCHEME 1.10.40. CYCLONEII_CONFIGURATION_SCHEME 1.10.41. CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION 1.10.42. CYCLONEII_TERMINATION 1.10.43. CYCLONE_CONFIGURATION_SCHEME 1.10.44. D1_DELAY 1.10.45. D1_FINE_DELAY 1.10.46. D2_DELAY 1.10.47. D3_DELAY 1.10.48. D4_DELAY 1.10.49. D4_FINE_DELAY 1.10.50. D5_DELAY 1.10.51. D5_FINE_DELAY 1.10.52. D5_OCT_DELAY 1.10.53. D5_OE_DELAY 1.10.54. D6_DELAY 1.10.55. D6_FINE_DELAY 1.10.56. D6_OCT_DELAY 1.10.57. D6_OE_DELAY 1.10.58. D6_OE_FINE_DELAY 1.10.59. DATA0_PIN 1.10.60. DCLK_PIN 1.10.61. DC_CURRENT_FOR_ELECTROMIGRATION_CHECK 1.10.62. DDIO_INPUT_REGISTER 1.10.63. DDIO_OUTPUT_REGISTER 1.10.64. DDIO_OUTPUT_REGISTER_DISTANCE 1.10.65. DECREASE_INPUT_DELAY_TO_INPUT_REGISTER 1.10.66. DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER 1.10.67. DELAY_SETTING_FROM_VIO_TO_CORE 1.10.68. DEVICE 1.10.69. DEVICE_INITIALIZATION_CLOCK 1.10.70. DEVICE_MIGRATION_LIST 1.10.71. DEVICE_TECHNOLOGY_MIGRATION_LIST 1.10.72. DM_PIN 1.10.73. DPRIO_CHANNEL_NUM 1.10.74. DPRIO_CRUCLK_NUM 1.10.75. DPRIO_INTERFACE_REG 1.10.76. DPRIO_QUAD_NUM 1.10.77. DPRIO_QUAD_PLL_NUM 1.10.78. DPRIO_TX_PLL0_REFCLK_NUM 1.10.79. DPRIO_TX_PLL1_REFCLK_NUM 1.10.80. DPRIO_TX_PLL_NUM 1.10.81. DQSB_DQS_PAIR 1.10.82. DQSOUT_DELAY_CHAIN 1.10.83. DQS_ENABLE_DELAY_CHAIN 1.10.84. DQS_LOCAL_CLOCK_DELAY_CHAIN 1.10.85. DQ_GROUP 1.10.86. DQ_PIN 1.10.87. DUAL_PURPOSE_CLOCK_PIN_DELAY 1.10.88. DUPLICATE_ATOM 1.10.89. DYNAMIC_OCT_CONTROL_GROUP 1.10.90. ECO_ALLOW_ROUTING_CHANGES 1.10.91. ECO_OPTIMIZE_TIMING 1.10.92. ECO_REGENERATE_REPORT 1.10.93. ENABLE_ASMI_FOR_FLASH_LOADER 1.10.94. ENABLE_BENEFICIAL_SKEW_OPTIMIZATION 1.10.95. ENABLE_BOOT_SEL_PIN 1.10.96. ENABLE_BUS_HOLD_CIRCUITRY 1.10.97. ENABLE_CONFIGURATION_PINS 1.10.98. ENABLE_CRC_ERROR_PIN 1.10.99. ENABLE_CVP_CONFDONE 1.10.100. ENABLE_DEVICE_WIDE_OE 1.10.101. ENABLE_DEVICE_WIDE_RESET 1.10.102. ENABLE_HOLD_BACK_OFF 1.10.103. ENABLE_INIT_DONE_OUTPUT 1.10.104. ENABLE_JTAG_BST_SUPPORT 1.10.105. ENABLE_JTAG_PIN_SHARING 1.10.106. ENABLE_NCEO_OUTPUT 1.10.107. ENABLE_NCE_PIN 1.10.108. ENABLE_NCONFIG_FROM_CORE 1.10.109. ENABLE_PR_PINS 1.10.110. ENABLE_UNUSED_RX_CLOCK_WORKAROUND 1.10.111. ENABLE_VREFA_PIN 1.10.112. ENABLE_VREFB_PIN 1.10.113. ERROR_CHECK_FREQUENCY_DIVISOR 1.10.114. EXCLUSIVE_IO_GROUP 1.10.115. EXTERNAL_LVDS_RX_USES_DPA 1.10.116. FASTROW_INTERCONNECT 1.10.117. FINAL_PLACEMENT_OPTIMIZATION 1.10.118. FITTER_ADJUST_HC_SHORT_PATH_GUARDBAND 1.10.119. FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION 1.10.120. FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 1.10.121. FITTER_EARLY_TIMING_ESTIMATE_MODE 1.10.122. FITTER_EFFORT 1.10.123. FIT_ATTEMPTS_TO_SKIP 1.10.124. FIT_ONLY_ONE_ATTEMPT 1.10.125. FLEX10K_CONFIGURATION_SCHEME 1.10.126. FLEX10K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS 1.10.127. FLEX10K_DEVICE_IO_STANDARD 1.10.128. FLEX10K_ENABLE_LOCK_OUTPUT 1.10.129. FLEX10K_MAX_PERIPHERAL_OE 1.10.130. FLEX6K_CONFIGURATION_SCHEME 1.10.131. FLEX6K_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS 1.10.132. FLEX6K_DEVICE_IO_STANDARD 1.10.133. FORCE_CONFIGURATION_VCCIO 1.10.134. FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS 1.10.135. FORCE_FRACTURED_MODE_ALM_IMPLEMENTATION 1.10.136. FORCE_MERGE_PLL 1.10.137. FORCE_MERGE_PLL_FANOUTS 1.10.138. FORCE_NON_FRACTURED_MODE_ALM_IMPLEMENTATION 1.10.139. FORM_DDR_CLUSTERING_CLIQUE 1.10.140. GENERATE_GXB_RECONFIG_MIF 1.10.141. GENERATE_GXB_RECONFIG_MIF_WITH_PLL 1.10.142. GLOBAL_SIGNAL 1.10.143. GLOBAL_SIGNAL_CLKCTRL_LOCATION 1.10.144. GNDIO_CURRENT_1PT8V 1.10.145. GNDIO_CURRENT_2PT5V 1.10.146. GNDIO_CURRENT_GTL 1.10.147. GNDIO_CURRENT_GTL_PLUS 1.10.148. GNDIO_CURRENT_LVCMOS 1.10.149. GNDIO_CURRENT_LVTTL 1.10.150. GNDIO_CURRENT_PCI 1.10.151. GNDIO_CURRENT_SSTL2_CLASS1 1.10.152. GNDIO_CURRENT_SSTL2_CLASS2 1.10.153. GNDIO_CURRENT_SSTL3_CLASS1 1.10.154. GNDIO_CURRENT_SSTL3_CLASS2 1.10.155. GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME 1.10.156. GXB_0PPM_CLOCK_GROUP 1.10.157. GXB_0PPM_CLOCK_GROUP_DRIVER 1.10.158. GXB_0PPM_CORECLK 1.10.159. GXB_0PPM_CORE_CLOCK 1.10.160. GXB_CLOCK_GROUP 1.10.161. GXB_CLOCK_GROUP_DRIVER 1.10.162. GXB_RECONFIG_GROUP 1.10.163. GXB_RECONFIG_MIF 1.10.164. GXB_RECONFIG_MIF_PLL 1.10.165. GXB_REFCLK_COUPLING_TERMINATION_SETTING 1.10.166. GXB_RESERVED_TRANSMIT_CHANNEL 1.10.167. GXB_TX_PLL_RECONFIG_GROUP 1.10.168. HPS_IO 1.10.169. IGNORE_HSSI_COLUMN_POWER_WHEN_PRESERVING_UNUSED_XCVR_CHANNELS 1.10.170. IGNORE_MODE_FOR_MERGE 1.10.171. IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE 1.10.172. INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN 1.10.173. INCREASE_DELAY_TO_OUTPUT_PIN 1.10.174. INCREASE_INPUT_CLOCK_ENABLE_DELAY 1.10.175. INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER 1.10.176. INCREASE_OUTPUT_CLOCK_ENABLE_DELAY 1.10.177. INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY 1.10.178. INCREASE_TZX_DELAY_TO_OUTPUT_PIN 1.10.179. INC_PLC_MODE 1.10.180. INIT_DONE_OPEN_DRAIN 1.10.181. INPUT_DELAY_CHAIN 1.10.182. INPUT_REFERENCE 1.10.183. INPUT_TERMINATION 1.10.184. INSERT_ADDITIONAL_LOGIC_CELL 1.10.185. INTERNAL_FLASH_UPDATE_MODE 1.10.186. INTERNAL_SCRUBBING 1.10.187. IO_12_LANE_INPUT_DATA_DELAY_CHAIN 1.10.188. IO_12_LANE_INPUT_STROBE_DELAY_CHAIN 1.10.189. IO_MAXIMUM_TOGGLE_RATE 1.10.190. IO_PLACEMENT_OPTIMIZATION 1.10.191. IO_STANDARD 1.10.192. LVDS_DIRECT_LOOPBACK_MODE 1.10.193. LVDS_RX_REGISTER 1.10.194. M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY 1.10.195. MACRO_HEAD 1.10.196. MACRO_MEMBER 1.10.197. MATCH_PLL_COMPENSATION_CLOCK 1.10.198. MAX10FPGA_CONFIGURATION_SCHEME 1.10.199. MAX7000B_VCCIO_IOBANK1 1.10.200. MAX7000B_VCCIO_IOBANK2 1.10.201. MAX7000_DEVICE_IO_STANDARD 1.10.202. MAX7000_ENABLE_JTAG_BST_SUPPORT 1.10.203. MAX7000_INDIVIDUAL_TURBO_BIT 1.10.204. MAX_CLOCKS_ALLOWED 1.10.205. MAX_CONSECUTIVE_OUTPUTS_FOR_ELECTROMIGRATION 1.10.206. MAX_CONSECUTIVE_VIO_OUTPUTS_FOR_ELECTROMIGRATION 1.10.207. MAX_CURRENT_FOR_ELECTROMIGRATION 1.10.208. MAX_CURRENT_FOR_VIO_ELECTROMIGRATION 1.10.209. MAX_GLOBAL_CLOCKS_ALLOWED 1.10.210. MAX_PERIPHERY_CLOCKS_ALLOWED 1.10.211. MAX_REGIONAL_CLOCKS_ALLOWED 1.10.212. MEMORY_INTERFACE_DATA_PIN_GROUP 1.10.213. MEM_INTERFACE_DELAY_CHAIN_CONFIG 1.10.214. MERCURY_CONFIGURATION_SCHEME 1.10.215. MERCURY_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS 1.10.216. MERCURY_DEVICE_IO_STANDARD 1.10.217. MERGE_TX_PLL_DRIVEN_BY_REGISTERS_WITH_SAME_CLEAR 1.10.218. MIGRATION_CONSTRAIN_CORE_RESOURCES 1.10.219. MIGRATION_DEVICES 1.10.220. NCEO_OPEN_DRAIN 1.10.221. NDQS_LOCAL_CLOCK_DELAY_CHAIN 1.10.222. NORMAL_LCELL_INSERT 1.10.223. OE_DELAY_CHAIN 1.10.224. OPTIMIZE_FOR_METASTABILITY 1.10.225. OPTIMIZE_HOLD_TIMING 1.10.226. OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING 1.10.227. OPTIMIZE_MULTI_CORNER_TIMING 1.10.228. OPTIMIZE_POWER_DURING_FITTING 1.10.229. OPTIMIZE_SSN 1.10.230. OPTIMIZE_TIMING 1.10.231. OUTPUT_BUFFER_DELAY 1.10.232. OUTPUT_BUFFER_DELAY_CONTROL 1.10.233. OUTPUT_DELAY_CHAIN 1.10.234. OUTPUT_ENABLE_DELAY 1.10.235. OUTPUT_ENABLE_GROUP 1.10.236. OUTPUT_ENABLE_REGISTER_DUPLICATION 1.10.237. OUTPUT_ENABLE_ROUTING 1.10.238. OUTPUT_PIN_LOAD 1.10.239. OUTPUT_TERMINATION 1.10.240. OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS 1.10.241. PAD_TO_CORE_DELAY 1.10.242. PAD_TO_DDIO_REGISTER_DELAY 1.10.243. PAD_TO_INPUT_REGISTER_DELAY 1.10.244. PCI_IO 1.10.245. PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION 1.10.246. PERIPH_FITTER_SCRIPT 1.10.247. PERIPH_REPORT_SCRIPT 1.10.248. PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING 1.10.249. PHYSICAL_SYNTHESIS_COMBO_LOGIC 1.10.250. PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA 1.10.251. PHYSICAL_SYNTHESIS_EFFORT 1.10.252. PHYSICAL_SYNTHESIS_LOG_FILE 1.10.253. PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA 1.10.254. PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION 1.10.255. PHYSICAL_SYNTHESIS_REGISTER_RETIMING 1.10.256. PLACEMENT_EFFORT_MULTIPLIER 1.10.257. PLL_AUTO_RESET 1.10.258. PLL_BANDWIDTH_PRESET 1.10.259. PLL_CHANNEL_SPACING 1.10.260. PLL_COMPENSATE 1.10.261. PLL_COMPENSATION_MODE 1.10.262. PLL_ENFORCE_USER_PHASE_SHIFT 1.10.263. PLL_FEEDBACK_CLOCK_SIGNAL 1.10.264. PLL_FORCE_OUTPUT_COUNTER 1.10.265. PLL_FORCE_OUTPUT_COUNTER_HARDCOPY_REPLAY 1.10.266. PLL_IGNORE_MIGRATION_DEVICES 1.10.267. PLL_OPTIMIZE_PHASE_SHIFT_FOR_TIMING 1.10.268. PLL_OUTPUT_CLOCK_FREQUENCY 1.10.269. PLL_PFD_CLOCK_FREQUENCY 1.10.270. PLL_TYPE 1.10.271. PLL_VCO_CLOCK_FREQUENCY 1.10.272. PRESERVE_PLL_COUNTER_ORDER 1.10.273. PRESERVE_UNUSED_XCVR_CHANNEL 1.10.274. PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.10.275. PROGRAMMABLE_POWER_TECHNOLOGY_SETTING 1.10.276. PROGRAMMABLE_PREEMPHASIS 1.10.277. PROGRAMMABLE_VOD 1.10.278. PR_DONE_OPEN_DRAIN 1.10.279. PR_ERROR_OPEN_DRAIN 1.10.280. PR_PINS_OPEN_DRAIN 1.10.281. PR_READY_OPEN_DRAIN 1.10.282. QDR_D_PIN_GROUP 1.10.283. QII_AUTO_PACKED_REGISTERS 1.10.284. RELATIVE_NEUTRON_FLUX 1.10.285. RESERVE_ALL_UNUSED_PINS 1.10.286. RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP 1.10.287. RESERVE_ASDO_AFTER_CONFIGURATION 1.10.288. RESERVE_DATA0_AFTER_CONFIGURATION 1.10.289. RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION 1.10.290. RESERVE_DATA1_AFTER_CONFIGURATION 1.10.291. RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION 1.10.292. RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION 1.10.293. RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION 1.10.294. RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION 1.10.295. RESERVE_DCLK_AFTER_CONFIGURATION 1.10.296. RESERVE_FLASH_NCE_AFTER_CONFIGURATION 1.10.297. RESERVE_FLEXIBLE_CLOCK_NETWORK 1.10.298. RESERVE_NCEO_AFTER_CONFIGURATION 1.10.299. RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION 1.10.300. RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION 1.10.301. RESERVE_PR_PINS 1.10.302. RESERVE_RDYNBUSY_AFTER_CONFIGURATION 1.10.303. RESERVE_ROUTING_OUTPUT_FLEXIBILITY 1.10.304. ROUTER_CLOCKING_TOPOLOGY_ANALYSIS 1.10.305. ROUTER_EFFORT_MULTIPLIER 1.10.306. ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION 1.10.307. ROUTER_REGISTER_DUPLICATION 1.10.308. ROUTER_TIMING_OPTIMIZATION_LEVEL 1.10.309. ROW_GLOBAL_SIGNAL 1.10.310. RZQ_GROUP 1.10.311. SCE_PIN 1.10.312. SDO_PIN 1.10.313. SEED 1.10.314. SEU_FIT_REPORT 1.10.315. SLEW_RATE 1.10.316. SLOW_SLEW_RATE 1.10.317. SPECTRAQ_PHYSICAL_SYNTHESIS 1.10.318. STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET 1.10.319. STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE 1.10.320. STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE 1.10.321. STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B 1.10.322. STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER 1.10.323. STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE 1.10.324. STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE 1.10.325. STRATIXGX_ALLOW_POST8B10B_LOOPBACK 1.10.326. STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK 1.10.327. STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE 1.10.328. STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS 1.10.329. STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE 1.10.330. STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER 1.10.331. STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE 1.10.332. STRATIXGX_TERMINATION_VALUE 1.10.333. STRATIXIIGX_TERMINATION_VALUE 1.10.334. STRATIXIII_CONFIGURATION_SCHEME 1.10.335. STRATIXIII_MRAM_COMPATIBILITY 1.10.336. STRATIXIII_UPDATE_MODE 1.10.337. STRATIXII_CONFIGURATION_SCHEME 1.10.338. STRATIXII_TERMINATION 1.10.339. STRATIXV_CONFIGURATION_SCHEME 1.10.340. STRATIX_CONFIGURATION_SCHEME 1.10.341. STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS 1.10.342. STRATIX_DEVICE_IO_STANDARD 1.10.343. STRATIX_UPDATE_MODE 1.10.344. SYNCHRONIZER_IDENTIFICATION 1.10.345. SYNCHRONIZER_TOGGLE_RATE 1.10.346. T11_0_DELAY 1.10.347. T11_1_DELAY 1.10.348. T11_DELAY 1.10.349. T11_FINE_DELAY 1.10.350. T4_DELAY 1.10.351. T8_DELAY0 1.10.352. T8_DELAY1 1.10.353. TERMINATION 1.10.354. TERMINATION_CONTROL_BLOCK 1.10.355. TREAT_BIDIR_AS_OUTPUT 1.10.356. TRI_STATE_SPI_PINS 1.10.357. TURBO_BIT 1.10.358. TXPMA_SLEW_RATE 1.10.359. UNFORCE_MERGE_PLL 1.10.360. UNFORCE_MERGE_PLL_OUTPUT_COUNTER 1.10.361. UNUSED_TSD_PINS_GND 1.10.362. USER_START_UP_CLOCK 1.10.363. VCCIO_CURRENT_1PT8V 1.10.364. VCCIO_CURRENT_2PT5V 1.10.365. VCCIO_CURRENT_GTL 1.10.366. VCCIO_CURRENT_GTL_PLUS 1.10.367. VCCIO_CURRENT_LVCMOS 1.10.368. VCCIO_CURRENT_LVTTL 1.10.369. VCCIO_CURRENT_PCI 1.10.370. VCCIO_CURRENT_SSTL2_CLASS1 1.10.371. VCCIO_CURRENT_SSTL2_CLASS2 1.10.372. VCCIO_CURRENT_SSTL3_CLASS1 1.10.373. VCCIO_CURRENT_SSTL3_CLASS2 1.10.374. VCCPD_VOLTAGE 1.10.375. VREF_MODE 1.10.376. WEAK_PULL_UP_RESISTOR 1.10.377. XCVR_A10_REFCLK_TERM_TRISTATE 1.10.378. XCVR_A10_RX_ADP_CTLE_ACGAIN_4S 1.10.379. XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL 1.10.380. XCVR_A10_RX_ADP_DFE_FXTAP1 1.10.381. XCVR_A10_RX_ADP_DFE_FXTAP10 1.10.382. XCVR_A10_RX_ADP_DFE_FXTAP10_SGN 1.10.383. XCVR_A10_RX_ADP_DFE_FXTAP11 1.10.384. XCVR_A10_RX_ADP_DFE_FXTAP11_SGN 1.10.385. XCVR_A10_RX_ADP_DFE_FXTAP2 1.10.386. XCVR_A10_RX_ADP_DFE_FXTAP2_SGN 1.10.387. XCVR_A10_RX_ADP_DFE_FXTAP3 1.10.388. XCVR_A10_RX_ADP_DFE_FXTAP3_SGN 1.10.389. XCVR_A10_RX_ADP_DFE_FXTAP4 1.10.390. XCVR_A10_RX_ADP_DFE_FXTAP4_SGN 1.10.391. XCVR_A10_RX_ADP_DFE_FXTAP5 1.10.392. XCVR_A10_RX_ADP_DFE_FXTAP5_SGN 1.10.393. XCVR_A10_RX_ADP_DFE_FXTAP6 1.10.394. XCVR_A10_RX_ADP_DFE_FXTAP6_SGN 1.10.395. XCVR_A10_RX_ADP_DFE_FXTAP7 1.10.396. XCVR_A10_RX_ADP_DFE_FXTAP7_SGN 1.10.397. XCVR_A10_RX_ADP_DFE_FXTAP8 1.10.398. XCVR_A10_RX_ADP_DFE_FXTAP8_SGN 1.10.399. XCVR_A10_RX_ADP_DFE_FXTAP9 1.10.400. XCVR_A10_RX_ADP_DFE_FXTAP9_SGN 1.10.401. XCVR_A10_RX_ADP_VGA_SEL 1.10.402. XCVR_A10_RX_EQ_BW_SEL 1.10.403. XCVR_A10_RX_EQ_DC_GAIN_TRIM 1.10.404. XCVR_A10_RX_LINK 1.10.405. XCVR_A10_RX_ONE_STAGE_ENABLE 1.10.406. XCVR_A10_RX_TERM_SEL 1.10.407. XCVR_A10_TX_COMPENSATION_EN 1.10.408. XCVR_A10_TX_LINK 1.10.409. XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP 1.10.410. XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP 1.10.411. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T 1.10.412. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T 1.10.413. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 1.10.414. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP 1.10.415. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 1.10.416. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T 1.10.417. XCVR_A10_TX_SLEW_RATE_CTRL 1.10.418. XCVR_A10_TX_TERM_SEL 1.10.419. XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 1.10.420. XCVR_A10_TX_XTX_PATH_ANALOG_MODE 1.10.421. XCVR_ANALOG_SETTINGS_PROTOCOL 1.10.422. XCVR_GT_IO_PIN_TERMINATION 1.10.423. XCVR_GT_RX_COMMON_MODE_VOLTAGE 1.10.424. XCVR_GT_RX_CTLE 1.10.425. XCVR_GT_RX_DC_GAIN 1.10.426. XCVR_GT_TX_COMMON_MODE_VOLTAGE 1.10.427. XCVR_GT_TX_PRE_EMP_1ST_POST_TAP 1.10.428. XCVR_GT_TX_PRE_EMP_INV_PRE_TAP 1.10.429. XCVR_GT_TX_PRE_EMP_PRE_TAP 1.10.430. XCVR_GT_TX_VOD_MAIN_TAP 1.10.431. XCVR_IO_PIN_TERMINATION 1.10.432. XCVR_RECONFIG_GROUP 1.10.433. XCVR_REFCLK_PIN_TERMINATION 1.10.434. XCVR_RX_ACGAIN_A 1.10.435. XCVR_RX_ACGAIN_V 1.10.436. XCVR_RX_BYPASS_EQ_STAGES_234 1.10.437. XCVR_RX_COMMON_MODE_VOLTAGE 1.10.438. XCVR_RX_DC_GAIN 1.10.439. XCVR_RX_ENABLE_LINEAR_EQUALIZER_PCIEMODE 1.10.440. XCVR_RX_EQ_BW_SEL 1.10.441. XCVR_RX_INPUT_VCM_SEL 1.10.442. XCVR_RX_LINEAR_EQUALIZER_CONTROL 1.10.443. XCVR_RX_SD_ENABLE 1.10.444. XCVR_RX_SD_OFF 1.10.445. XCVR_RX_SD_ON 1.10.446. XCVR_RX_SD_THRESHOLD 1.10.447. XCVR_RX_SEL_HALF_BW 1.10.448. XCVR_TX_COMMON_MODE_VOLTAGE 1.10.449. XCVR_TX_PLL_RECONFIG_GROUP 1.10.450. XCVR_TX_PRE_EMP_1ST_POST_TAP 1.10.451. XCVR_TX_PRE_EMP_2ND_POST_TAP 1.10.452. XCVR_TX_PRE_EMP_2ND_POST_TAP_USER 1.10.453. XCVR_TX_PRE_EMP_INV_2ND_TAP 1.10.454. XCVR_TX_PRE_EMP_INV_PRE_TAP 1.10.455. XCVR_TX_PRE_EMP_PRE_TAP 1.10.456. XCVR_TX_PRE_EMP_PRE_TAP_USER 1.10.457. XCVR_TX_RX_DET_ENABLE 1.10.458. XCVR_TX_RX_DET_MODE 1.10.459. XCVR_TX_RX_DET_OUTPUT_SEL 1.10.460. XCVR_TX_SLEW_RATE_CTRL 1.10.461. XCVR_TX_VCM_CTRL_SRC 1.10.462. XCVR_TX_VOD 1.10.463. XCVR_TX_VOD_PRE_EMP_CTRL_SRC 1.10.464. XCVR_VCCA_VOLTAGE 1.10.465. XCVR_VCCR_VCCT_VOLTAGE 1.10.466. XSTL_INPUT_ALLOW_SE_BUFFER
1.11. Incremental Compilation Assignments x
1.11.1. ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS 1.11.2. ALLOW_MULTIPLE_PERSONAS 1.11.3. AUTO_EXPORT_INCREMENTAL_COMPILATION 1.11.4. CROSS_BOUNDARY_OPTIMIZATIONS 1.11.5. ENABLE_LAB_SHARING_WITH_PARENT_PARTITION 1.11.6. ENABLE_STRICT_PRESERVATION 1.11.7. EXTENDS_TOP_BLOCK 1.11.8. IGNORE_PARTITIONS 1.11.9. IMPORT_BLOCK 1.11.10. INCREMENTAL_COMPILATION_EXPORT_FILE 1.11.11. INCREMENTAL_COMPILATION_EXPORT_FLATTEN 1.11.12. INCREMENTAL_COMPILATION_EXPORT_PARTITION_NAME 1.11.13. INCREMENTAL_COMPILATION_EXPORT_POST_FIT 1.11.14. INCREMENTAL_COMPILATION_EXPORT_POST_SYNTH 1.11.15. INCREMENTAL_COMPILATION_EXPORT_ROUTING 1.11.16. INPUT_PERSONA 1.11.17. INSERT_BOUNDARY_WIRE_LUTS 1.11.18. MERGE_EQUIVALENT_BIDIRS 1.11.19. MERGE_EQUIVALENT_INPUTS 1.11.20. PARTIAL_RECONFIGURATION_PARTITION 1.11.21. PARTITION 1.11.22. PARTITION_ALWAYS_USE_QXP_NETLIST 1.11.23. PARTITION_ASD_REGION 1.11.24. PARTITION_ASD_REGION_ID 1.11.25. PARTITION_ENABLE_STRICT_PRESERVATION 1.11.26. PARTITION_FITTER_PRESERVATION_LEVEL 1.11.27. PARTITION_HIERARCHY 1.11.28. PARTITION_IGNORE_SOURCE_FILE_CHANGES 1.11.29. PARTITION_IMPORT_ASSIGNMENTS 1.11.30. PARTITION_IMPORT_EXISTING_ASSIGNMENTS 1.11.31. PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS 1.11.32. PARTITION_IMPORT_FILE 1.11.33. PARTITION_IMPORT_PROMOTE_ASSIGNMENTS 1.11.34. PARTITION_LAST_IMPORTED_FILE 1.11.35. PARTITION_NETLIST_TYPE 1.11.36. PARTITION_PRESERVE_HIGH_SPEED_TILES 1.11.37. PRESERVE 1.11.38. PROPAGATE_CONSTANTS_ON_INPUTS 1.11.39. PROPAGATE_INVERSIONS_ON_INPUTS 1.11.40. QDB_PATH 1.11.41. RAPID_RECOMPILE_ASSIGNMENT_CHECKING 1.11.42. REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS
1.12. LogicLock Region Assignments x
1.12.1. CORE_ONLY_PLACE_REGION 1.12.2. LL_AUTO_SIZE 1.12.3. LL_CORE_ONLY 1.12.4. LL_ENABLED 1.12.5. LL_HEIGHT 1.12.6. LL_MEMBER_EXCEPTIONS 1.12.7. LL_MEMBER_OF 1.12.8. LL_MEMBER_OF_SECURITY_ROUTING_INTERFACE 1.12.9. LL_ORIGIN 1.12.10. LL_PARENT 1.12.11. LL_PRIORITY 1.12.12. LL_RESERVED 1.12.13. LL_ROOT_REGION 1.12.14. LL_STATE 1.12.15. LL_WIDTH 1.12.16. PLACE_REGION 1.12.17. RESERVE_PLACE_REGION 1.12.18. ROUTE_REGION
1.13. Migration Assignments x
1.13.1. MIGRATION_AUTO_PACKED_REGISTERS 1.13.2. MIGRATION_AUTO_PORT_SWAP 1.13.3. MIGRATION_RAM_INFORMATION
1.14. Netlist Viewer Assignments x
1.14.1. RTLV_GROUP_COMB_LOGIC_IN_CLOUD 1.14.2. RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV 1.14.3. RTLV_GROUP_RELATED_NODES 1.14.4. RTLV_GROUP_RELATED_NODES_TMV 1.14.5. RTLV_REMOVE_FANOUT_FREE_REGISTERS 1.14.6. RTLV_SIMPLIFIED_LOGIC
1.15. Pin & Location Assignments x
1.15.1. APEX20K_CLIQUE_TYPE 1.15.2. APEX20K_LOCAL_ROUTING_SOURCE 1.15.3. FAST_INPUT_REGISTER 1.15.4. FAST_OCT_REGISTER 1.15.5. FAST_OUTPUT_ENABLE_REGISTER 1.15.6. FAST_OUTPUT_REGISTER 1.15.7. FLEX10K_CLIQUE_TYPE 1.15.8. FLEX6K_CLIQUE_TYPE 1.15.9. FLEX6K_LOCAL_ROUTING_SOURCE 1.15.10. IP_DEBUG_VISIBLE 1.15.11. LL_IGNORE_IO_PIN_SECURITY_CONSTRAINT 1.15.12. LOCATION 1.15.13. MAX7K_CLIQUE_TYPE 1.15.14. MEMBER_OF 1.15.15. MERCURY_CLIQUE_TYPE 1.15.16. PIN_CONNECT_FROM_NODE 1.15.17. RESERVE_PIN 1.15.18. SUBCLIQUE_OF 1.15.19. VIRTUAL_PIN
1.16. Power Estimation Assignments x
1.16.1. ENABLE_SMART_VOLTAGE_ID 1.16.2. POWER_AUTO_COMPUTE_TJ 1.16.3. POWER_BOARD_TEMPERATURE 1.16.4. POWER_BOARD_THERMAL_MODEL 1.16.5. POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 1.16.6. POWER_DEFAULT_TOGGLE_RATE 1.16.7. POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 1.16.8. POWER_GLITCH_FACTOR 1.16.9. POWER_HPS_DYNAMIC_POWER_DUAL 1.16.10. POWER_HPS_DYNAMIC_POWER_SINGLE 1.16.11. POWER_HPS_ENABLE 1.16.12. POWER_HPS_JUNCTION_TEMPERATURE 1.16.13. POWER_HPS_PROC_FREQ 1.16.14. POWER_HPS_STATIC_POWER 1.16.15. POWER_HPS_TOTAL_POWER 1.16.16. POWER_HSSI 1.16.17. POWER_HSSI_LEFT 1.16.18. POWER_HSSI_RIGHT 1.16.19. POWER_HSSI_VCCHIP_LEFT 1.16.20. POWER_HSSI_VCCHIP_RIGHT 1.16.21. POWER_INPUT_FILE_NAME 1.16.22. POWER_INPUT_FILE_TYPE 1.16.23. POWER_INPUT_SAF_NAME 1.16.24. POWER_INPUT_VCD_FILE_NAME 1.16.25. POWER_OCS_VALUE 1.16.26. POWER_OJB_VALUE 1.16.27. POWER_OJC_VALUE 1.16.28. POWER_OSA_VALUE 1.16.29. POWER_OUTPUT_SAF_NAME 1.16.30. POWER_PRESET_COOLING_SOLUTION 1.16.31. POWER_READ_INPUT_FILE 1.16.32. POWER_REPORT_POWER_DISSIPATION 1.16.33. POWER_REPORT_SIGNAL_ACTIVITY 1.16.34. POWER_SIGNAL_ACTIVITY_END_TIME 1.16.35. POWER_SIGNAL_ACTIVITY_START_TIME 1.16.36. POWER_STATIC_PROBABILITY 1.16.37. POWER_TJ_VALUE 1.16.38. POWER_TOGGLE_RATE 1.16.39. POWER_TOGGLE_RATE_PERCENTAGE 1.16.40. POWER_USE_CUSTOM_COOLING_SOLUTION 1.16.41. POWER_USE_DEVICE_CHARACTERISTICS 1.16.42. POWER_USE_INPUT_FILE 1.16.43. POWER_USE_INPUT_FILES 1.16.44. POWER_USE_PVA 1.16.45. POWER_USE_TA_VALUE 1.16.46. POWER_VCCAUX_USER_OPTION 1.16.47. POWER_VCCA_GXBL_USER_OPTION 1.16.48. POWER_VCCA_GXBR_USER_OPTION 1.16.49. POWER_VCCA_GXB_USER_OPTION 1.16.50. POWER_VCCA_L_USER_OPTION 1.16.51. POWER_VCCA_R_USER_OPTION 1.16.52. POWER_VCCCB_USER_OPTION 1.16.53. POWER_VCCH_GXBL_USER_OPTION 1.16.54. POWER_VCCH_GXBR_USER_OPTION 1.16.55. POWER_VCCH_GXB_USER_OPTION 1.16.56. POWER_VCCIO_USER_OPTION 1.16.57. POWER_VCCL_GXB_USER_OPTION 1.16.58. POWER_VCCPD_USER_OPTION 1.16.59. POWER_VCCR_GXBL_USER_OPTION 1.16.60. POWER_VCCR_GXBR_USER_OPTION 1.16.61. POWER_VCCR_GXB_USER_OPTION 1.16.62. POWER_VCCT_GXBL_USER_OPTION 1.16.63. POWER_VCCT_GXBR_USER_OPTION 1.16.64. POWER_VCCT_GXB_USER_OPTION 1.16.65. POWER_VCD_FILE_END_TIME 1.16.66. POWER_VCD_FILE_START_TIME 1.16.67. POWER_VCD_FILTER_GLITCHES 1.16.68. VCCAUX_SHARED_USER_VOLTAGE 1.16.69. VCCAUX_USER_VOLTAGE 1.16.70. VCCA_FPLL_USER_VOLTAGE 1.16.71. VCCA_GTBR_USER_VOLTAGE 1.16.72. VCCA_GTB_USER_VOLTAGE 1.16.73. VCCA_GXBL_USER_VOLTAGE 1.16.74. VCCA_GXBR_USER_VOLTAGE 1.16.75. VCCA_GXB_USER_VOLTAGE 1.16.76. VCCA_L_USER_VOLTAGE 1.16.77. VCCA_PLL_USER_VOLTAGE 1.16.78. VCCA_R_USER_VOLTAGE 1.16.79. VCCA_USER_VOLTAGE 1.16.80. VCCBAT_USER_VOLTAGE 1.16.81. VCCCB_USER_VOLTAGE 1.16.82. VCCD_FPLL_USER_VOLTAGE 1.16.83. VCCD_PLL_USER_VOLTAGE 1.16.84. VCCD_USER_VOLTAGE 1.16.85. VCCEH_GXBL_USER_VOLTAGE 1.16.86. VCCEH_GXBR_USER_VOLTAGE 1.16.87. VCCEH_GXB_USER_VOLTAGE 1.16.88. VCCERAM_USER_VOLTAGE 1.16.89. VCCE_GXBL_USER_VOLTAGE 1.16.90. VCCE_GXBR_USER_VOLTAGE 1.16.91. VCCE_GXB_USER_VOLTAGE 1.16.92. VCCE_USER_VOLTAGE 1.16.93. VCCHIP_L_USER_VOLTAGE 1.16.94. VCCHIP_R_USER_VOLTAGE 1.16.95. VCCHIP_USER_VOLTAGE 1.16.96. VCCHSSI_L_USER_VOLTAGE 1.16.97. VCCHSSI_R_USER_VOLTAGE 1.16.98. VCCH_GTBR_USER_VOLTAGE 1.16.99. VCCH_GTB_USER_VOLTAGE 1.16.100. VCCH_GXBL_USER_VOLTAGE 1.16.101. VCCH_GXBR_USER_VOLTAGE 1.16.102. VCCH_GXB_USER_VOLTAGE 1.16.103. VCCH_L_USER_VOLTAGE 1.16.104. VCCH_R_USER_VOLTAGE 1.16.105. VCCINT_USER_VOLTAGE 1.16.106. VCCIOREF_HPS_USER_VOLTAGE 1.16.107. VCCIO_HPS_USER_VOLTAGE 1.16.108. VCCIO_USER_VOLTAGE 1.16.109. VCCL_GTBL_USER_VOLTAGE 1.16.110. VCCL_GTBR_USER_VOLTAGE 1.16.111. VCCL_GTB_USER_VOLTAGE 1.16.112. VCCL_GXBL_USER_VOLTAGE 1.16.113. VCCL_GXBR_USER_VOLTAGE 1.16.114. VCCL_GXB_USER_VOLTAGE 1.16.115. VCCL_HPS_USER_VOLTAGE 1.16.116. VCCL_USER_VOLTAGE 1.16.117. VCCPD_USER_VOLTAGE 1.16.118. VCCPGM_USER_VOLTAGE 1.16.119. VCCPLL_HPS_USER_VOLTAGE 1.16.120. VCCPT_USER_VOLTAGE 1.16.121. VCCP_USER_VOLTAGE 1.16.122. VCCRSTCLK_HPS_USER_VOLTAGE 1.16.123. VCCR_GTBL_USER_VOLTAGE 1.16.124. VCCR_GTBR_USER_VOLTAGE 1.16.125. VCCR_GTB_USER_VOLTAGE 1.16.126. VCCR_GXBL_USER_VOLTAGE 1.16.127. VCCR_GXBR_USER_VOLTAGE 1.16.128. VCCR_GXB_USER_VOLTAGE 1.16.129. VCCR_L_USER_VOLTAGE 1.16.130. VCCR_R_USER_VOLTAGE 1.16.131. VCCR_USER_VOLTAGE 1.16.132. VCCT_GTBL_USER_VOLTAGE 1.16.133. VCCT_GTBR_USER_VOLTAGE 1.16.134. VCCT_GTB_USER_VOLTAGE 1.16.135. VCCT_GXBL_USER_VOLTAGE 1.16.136. VCCT_GXBR_USER_VOLTAGE 1.16.137. VCCT_GXB_USER_VOLTAGE 1.16.138. VCCT_L_USER_VOLTAGE 1.16.139. VCCT_R_USER_VOLTAGE 1.16.140. VCCT_USER_VOLTAGE 1.16.141. VCC_HPS_USER_VOLTAGE 1.16.142. VCC_USER_VOLTAGE
1.17. Programmer Assignments x
1.17.1. GENERATE_CONFIG_HEXOUT_FILE 1.17.2. GENERATE_CONFIG_ISC_FILE 1.17.3. GENERATE_CONFIG_JAM_FILE 1.17.4. GENERATE_CONFIG_JBC_FILE 1.17.5. GENERATE_CONFIG_JBC_FILE_COMPRESSED 1.17.6. GENERATE_CONFIG_SVF_FILE 1.17.7. GENERATE_ISC_FILE 1.17.8. GENERATE_JAM_FILE 1.17.9. GENERATE_JBC_FILE 1.17.10. GENERATE_JBC_FILE_COMPRESSED 1.17.11. GENERATE_SVF_FILE 1.17.12. HPS_EARLY_IO_RELEASE 1.17.13. ISP_CLAMP_STATE 1.17.14. ISP_CLAMP_STATE_DEFAULT 1.17.15. MERGE_HEX_FILE
1.18. Project-Wide Assignments x
1.18.1. AGGREGATE_REVISION 1.18.2. AHDL_FILE 1.18.3. AHDL_TEXT_DESIGN_OUTPUT_FILE 1.18.4. ASM_FILE 1.18.5. AUTO_EXPORT_VER_COMPATIBLE_DB 1.18.6. BASE_REVISION 1.18.7. BASE_REVISION_PROJECT_OUTPUT_DIRECTORY 1.18.8. BDF_FILE 1.18.9. BINARY_FILE 1.18.10. BSF_FILE 1.18.11. CDF_FILE 1.18.12. COMMAND_MACRO_FILE 1.18.13. CPP_FILE 1.18.14. CPP_INCLUDE_FILE 1.18.15. CUSP_FILE 1.18.16. CVP_REVISION 1.18.17. C_FILE 1.18.18. DEPENDENCY_FILE 1.18.19. DSPBUILDER_FILE 1.18.20. EDIF_FILE 1.18.21. ELF_FILE 1.18.22. ENABLE_COMPACT_REPORT_TABLE 1.18.23. ENABLE_REDUCED_MEMORY_MODE 1.18.24. EQUATION_FILE 1.18.25. FLOW_DISABLE_ASSEMBLER 1.18.26. FLOW_ENABLE_HC_COMPARE 1.18.27. FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS 1.18.28. FLOW_ENABLE_PARALLEL_MODULES 1.18.29. FLOW_ENABLE_POWER_ANALYZER 1.18.30. FLOW_ENABLE_RTL_VIEWER 1.18.31. FLOW_HARDCOPY_DESIGN_READINESS_CHECK 1.18.32. GDF_FILE 1.18.33. HC_OUTPUT_DIR 1.18.34. HEX_FILE 1.18.35. HEX_OUTPUT_FILE 1.18.36. HPS_ISW_FILE 1.18.37. HTML_FILE 1.18.38. HTML_REPORT_FILE 1.18.39. INCLUDE_FILE 1.18.40. IPA_FILE 1.18.41. IPX_FILE 1.18.42. IP_COMPONENT_AUTHOR 1.18.43. IP_COMPONENT_DESCRIPTION 1.18.44. IP_COMPONENT_DISPLAY_NAME 1.18.45. IP_COMPONENT_DOCUMENTATION_LINK 1.18.46. IP_COMPONENT_GROUP 1.18.47. IP_COMPONENT_INTERNAL 1.18.48. IP_COMPONENT_NAME 1.18.49. IP_COMPONENT_PARAMETER 1.18.50. IP_COMPONENT_REPORT_HIERARCHY 1.18.51. IP_COMPONENT_VERSION 1.18.52. IP_FILE 1.18.53. IP_GENERATED_DEVICE_FAMILY 1.18.54. IP_QSYS_MODE 1.18.55. IP_TARGETED_DEVICE_FAMILY 1.18.56. IP_TARGETED_PART_TRAIT 1.18.57. IP_TOOL_ENV 1.18.58. IP_TOOL_HIERARCHY_LEVELS 1.18.59. IP_TOOL_NAME 1.18.60. IP_TOOL_VERSION 1.18.61. ISC_FILE 1.18.62. JAM_FILE 1.18.63. JBC_FILE 1.18.64. LICENSE_FILE 1.18.65. LMF_FILE 1.18.66. LOGIC_ANALYZER_INTERFACE_FILE 1.18.67. MAP_FILE 1.18.68. MASK_REVISION 1.18.69. MESSAGE_DISABLE 1.18.70. MESSAGE_ENABLE 1.18.71. MIF_FILE 1.18.72. MIGRATION_DIFFERENT_SOURCE_FILE 1.18.73. MISC_FILE 1.18.74. NUM_PARALLEL_PROCESSORS 1.18.75. OBJECT_FILE 1.18.76. OCP_FILE 1.18.77. PARTIAL_SRAM_OBJECT_FILE 1.18.78. PDC_FILE 1.18.79. PERSONA_FILE 1.18.80. PIN_FILE 1.18.81. POWER_INPUT_FILE 1.18.82. PPF_FILE 1.18.83. PROGRAMMER_OBJECT_FILE 1.18.84. PROJECT_OUTPUT_DIRECTORY 1.18.85. PROJECT_SHOW_ENTITY_NAME 1.18.86. PROJECT_USE_SIMPLIFIED_NAMES 1.18.87. QARLOG_FILE 1.18.88. QAR_FILE 1.18.89. QDB_FILE 1.18.90. QIP_FILE 1.18.91. QSYS_FILE 1.18.92. QUARTUS_PTF_FILE 1.18.93. QUARTUS_SBD_FILE 1.18.94. QUARTUS_STANDARD_DELAY_FILE 1.18.95. QVAR_FILE 1.18.96. QXP_FILE 1.18.97. RAW_BINARY_FILE 1.18.98. READ_OR_WRITE_IN_BYTE_ADDRESS 1.18.99. RECONFIGURABLE_REVISION 1.18.100. REVISION_TYPE 1.18.101. RUN_FULL_COMPILE_ON_DEVICE_CHANGE 1.18.102. SAVE_MIGRATION_INFO_DURING_COMPILATION 1.18.103. SBI_FILE 1.18.104. SDC_ENTITY_FILE 1.18.105. SDC_ENTITY_HELPER_FILE 1.18.106. SDC_FILE 1.18.107. SDF_OUTPUT_FILE 1.18.108. SERIAL_BITSTREAM_FILE 1.18.109. SIGNALTAP_FILE 1.18.110. SIP_FILE 1.18.111. SLD_FILE 1.18.112. SMF_FILE 1.18.113. SOFTWARE_LIBRARY_FILE 1.18.114. SOPCINFO_FILE 1.18.115. SOPC_FILE 1.18.116. SOURCE_TCL_SCRIPT_FILE 1.18.117. SPD_FILE 1.18.118. SRAM_OBJECT_FILE 1.18.119. SRECORDS_FILE 1.18.120. SVF_FILE 1.18.121. SYM_FILE 1.18.122. SYNTHESIS_ONLY_QIP 1.18.123. SYSTEMVERILOG_FILE 1.18.124. TCL_ENTITY_FILE 1.18.125. TCL_SCRIPT_FILE 1.18.126. TEMPLATE_FILE 1.18.127. TEXT_FILE 1.18.128. TEXT_FORMAT_REPORT_FILE 1.18.129. TIMING_ANALYSIS_OUTPUT_FILE 1.18.130. VCD_FILE 1.18.131. VECTOR_TABLE_OUTPUT_FILE 1.18.132. VECTOR_TEXT_FILE 1.18.133. VECTOR_WAVEFORM_FILE 1.18.134. VERILOG_FILE 1.18.135. VERILOG_INCLUDE_FILE 1.18.136. VERILOG_OUTPUT_FILE 1.18.137. VERILOG_TEST_BENCH_FILE 1.18.138. VER_COMPATIBLE_DB_DIR 1.18.139. VHDL_FILE 1.18.140. VHDL_OUTPUT_FILE 1.18.141. VHDL_TEST_BENCH_FILE 1.18.142. VQM_FILE 1.18.143. ZIP_VECTOR_WAVEFORM_FILE
1.19. SignalProbe Assignments x
1.19.1. SIGNALPROBE_ALLOW_OVERUSE 1.19.2. SIGNALPROBE_CLOCK 1.19.3. SIGNALPROBE_DURING_NORMAL_COMPILATION 1.19.4. SIGNALPROBE_ENABLE 1.19.5. SIGNALPROBE_NUM_REGISTERS 1.19.6. SIGNALPROBE_SOURCE
1.20. SignalTap II Assignments x
1.20.1. ENABLE_LOGIC_ANALYZER_INTERFACE 1.20.2. ENABLE_SIGNALTAP 1.20.3. STP_FILE 1.20.4. USE_LOGIC_ANALYZER_INTERFACE_FILE 1.20.5. USE_SIGNALTAP_FILE
1.21. Simulator Assignments x
1.21.1. ACTION 1.21.2. ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS 1.21.3. ADD_TO_SIMULATION_OUTPUT_WAVEFORMS 1.21.4. ALIAS 1.21.5. AUTO_USE_SIMULATION_PDB_NETLIST 1.21.6. BREAKPOINT_STATE 1.21.7. CHECK_OUTPUTS 1.21.8. END_TIME 1.21.9. EXTERNAL_PIN_CONNECTION 1.21.10. GLITCH_DETECTION 1.21.11. GLITCH_INTERVAL 1.21.12. IMMEDIATE_ASSERTION_FAIL_ACTION 1.21.13. IMMEDIATE_ASSERTION_FAIL_MESSAGE 1.21.14. IMMEDIATE_ASSERTION_PASS_MESSAGE 1.21.15. IMMEDIATE_ASSERTION_STATE 1.21.16. IMMEDIATE_ASSERTION_TEST_CONDITION 1.21.17. INCREMENTAL_VECTOR_INPUT_SOURCE 1.21.18. PASSIVE_RESISTOR 1.21.19. SETUP_HOLD_DETECTION 1.21.20. SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED 1.21.21. SETUP_HOLD_TIME_VIOLATION_DETECTION 1.21.22. SIMULATION_BUS_CHANNEL_GROUPING 1.21.23. SIMULATION_CELL_DELAY_MODEL_TYPE 1.21.24. SIMULATION_COMPARE_SIGNAL 1.21.25. SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL 1.21.26. SIMULATION_COVERAGE 1.21.27. SIMULATION_DEFAULT_VECTOR_COMPARE_TOLERANCE 1.21.28. SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE 1.21.29. SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL 1.21.30. SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL 1.21.31. SIMULATION_MODE 1.21.32. SIMULATION_NETLIST_VIEWER 1.21.33. SIMULATION_SIGNAL_COMPARE_TOLERANCE 1.21.34. SIMULATION_VDB_RESULT_FLUSH 1.21.35. SIMULATION_VECTOR_COMPARE_BEGIN_TIME 1.21.36. SIMULATION_VECTOR_COMPARE_END_TIME 1.21.37. SIMULATION_VECTOR_COMPARE_RULE_FOR_0 1.21.38. SIMULATION_VECTOR_COMPARE_RULE_FOR_1 1.21.39. SIMULATION_VECTOR_COMPARE_RULE_FOR_DC 1.21.40. SIMULATION_VECTOR_COMPARE_RULE_FOR_H 1.21.41. SIMULATION_VECTOR_COMPARE_RULE_FOR_L 1.21.42. SIMULATION_VECTOR_COMPARE_RULE_FOR_U 1.21.43. SIMULATION_VECTOR_COMPARE_RULE_FOR_W 1.21.44. SIMULATION_VECTOR_COMPARE_RULE_FOR_X 1.21.45. SIMULATION_VECTOR_COMPARE_RULE_FOR_Z 1.21.46. SIMULATION_WITH_AUTO_GLITCH_FILTERING 1.21.47. SIMULATION_WITH_GLITCH_FILTERING_IN_NORMAL_FLOW 1.21.48. SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF 1.21.49. SIMULATOR_GENERATE_POWERPLAY_VCD_FILE 1.21.50. SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE 1.21.51. SIMULATOR_POWERPLAY_VCD_FILE_END_TIME 1.21.52. SIMULATOR_POWERPLAY_VCD_FILE_OUTPUT_DESTINATION 1.21.53. SIMULATOR_POWERPLAY_VCD_FILE_START_TIME 1.21.54. SIMULATOR_PVT_TIMING_MODEL_TYPE 1.21.55. SIMULATOR_SIGNAL_ACTIVITY_FILE_END_TIME 1.21.56. SIMULATOR_SIGNAL_ACTIVITY_FILE_OUTPUT_DESTINATION 1.21.57. SIMULATOR_SIGNAL_ACTIVITY_FILE_START_TIME 1.21.58. SIM_BEHAVIOR_SIMULATION 1.21.59. SIM_COMPILE_HDL_FILES 1.21.60. SIM_HDL_TOP_MODULE_NAME 1.21.61. SIM_OVERWRITE_WAVEFORM_INPUTS 1.21.62. SIM_TAP_REGISTER_D_Q_PORTS 1.21.63. SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 1.21.64. SIM_VECTOR_COMPARED_CLOCK_OFFSET 1.21.65. SIM_VECTOR_COMPARED_CLOCK_PERIOD 1.21.66. START_TIME 1.21.67. TRIGGER_EQUATION 1.21.68. TRIGGER_VECTOR_COMPARE_ON_SIGNAL 1.21.69. USER_MESSAGE 1.21.70. VECTOR_COMPARE_TRIGGER_MODE 1.21.71. VECTOR_INPUT_SOURCE 1.21.72. VECTOR_OUTPUT_DESTINATION 1.21.73. VECTOR_OUTPUT_FORMAT 1.21.74. X_ON_VIOLATION_OPTION
1. Altera® Quartus® Prime Standard Edition Settings File Reference Manual

1.2.77. IGNORE_VERILOG_INITIAL_CONSTRUCTS

Instructs Analysis & Synthesis to ignore initial constructs and variable declaration assignments in your Verilog HDL design files. By default, Analysis & Synthesis derives power-up conditions for your design by elaborating these constructs. This option is provided for backwards compatibility with previous versions of the Quartus Prime software that ignored these constructs by default. You can use this option to restore the previous behavior of your design in the current version of the software.

Type

Boolean

Device Support

This setting can be used in projects targeting any Altera device family.

Notes

This assignment is included in the Analysis & Synthesis report.

This assignment supports synthesis wildcards.

Syntax


		set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS <value>
		set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS -entity <entity name> <value>
		set_instance_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS -to <to> -entity <entity name> <value>

Default Value

Off

Example


		set_global_assignment -name ignore_verilog_initial_constructs off
Level Two Title