Arria® V Device Datasheet

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ID 683022
Date 5/23/2023
Public
Document Table of Contents
Document Table of Contents x
1. Arria® V GX, GT, SX, and ST Device Datasheet 2. Arria V GZ Device Datasheet
1. Arria® V GX, GT, SX, and ST Device Datasheet x
1.1. Electrical Characteristics 1.2. Switching Characteristics 1.3. Configuration Specifications 1.4. I/O Timing 1.5. Glossary 1.6. Arria® V GX, GT, SX, and ST Device Datasheet Revision History
1.1. Electrical Characteristics x
1.1.1. Operating Conditions
1.1.1. Operating Conditions x
1.1.1.1. Absolute Maximum Ratings 1.1.1.2. Maximum Allowed Overshoot and Undershoot Voltage 1.1.1.3. Recommended Operating Conditions 1.1.1.4. DC Characteristics 1.1.1.5. I/O Standard Specifications
1.1.1.3. Recommended Operating Conditions x
1.1.1.3.1. Recommended Operating Conditions 1.1.1.3.2. Transceiver Power Supply Operating Conditions 1.1.1.3.3. HPS Power Supply Operating Conditions
1.1.1.4. DC Characteristics x
1.1.1.4.1. Supply Current and Power Consumption 1.1.1.4.2. I/O Pin Leakage Current 1.1.1.4.3. Bus Hold Specifications 1.1.1.4.4. OCT Calibration Accuracy Specifications 1.1.1.4.5. OCT Without Calibration Resistance Tolerance Specifications 1.1.1.4.6. OCT Variation after Power-Up Calibration 1.1.1.4.7. Pin Capacitance 1.1.1.4.8. Hot Socketing 1.1.1.4.9. Internal Weak Pull-Up Resistor
1.1.1.5. I/O Standard Specifications x
1.1.1.5.1. Single-Ended I/O Standards 1.1.1.5.2. Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications 1.1.1.5.3. Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications 1.1.1.5.4. Differential SSTL I/O Standards 1.1.1.5.5. Differential HSTL and HSUL I/O Standards 1.1.1.5.6. Differential I/O Standard Specifications
1.2. Switching Characteristics x
1.2.1. Transceiver Performance Specifications 1.2.2. Core Performance Specifications 1.2.3. Periphery Performance 1.2.4. HPS Specifications
1.2.1. Transceiver Performance Specifications x
1.2.1.1. Transceiver Specifications for Arria V GX and SX Devices 1.2.1.2. Transceiver Specifications for Arria V GT and ST Devices 1.2.1.3. CTLE Response at Data Rates > 3.25 Gbps across Supported AC Gain and DC Gain 1.2.1.4. CTLE Response at Data Rates ≤ 3.25 Gbps across Supported AC Gain and DC Gain 1.2.1.5. Typical TX VOD Setting for Arria® V Transceiver Channels with termination of 100 Ω 1.2.1.6. Transmitter Pre-Emphasis Levels 1.2.1.7. Transceiver Compliance Specification
1.2.2. Core Performance Specifications x
1.2.2.1. Clock Tree Specifications 1.2.2.2. PLL Specifications 1.2.2.3. DSP Block Performance Specifications 1.2.2.4. Memory Block Performance Specifications 1.2.2.5. Internal Temperature Sensing Diode Specifications
1.2.3. Periphery Performance x
1.2.3.1. High-Speed I/O Specifications 1.2.3.2. DPA Lock Time Specifications 1.2.3.3. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications 1.2.3.4. DLL Frequency Range Specifications 1.2.3.5. DQS Logic Block Specifications 1.2.3.6. Memory Output Clock Jitter Specifications 1.2.3.7. OCT Calibration Block Specifications 1.2.3.8. Duty Cycle Distortion (DCD) Specifications
1.2.4. HPS Specifications x
1.2.4.1. HPS Clock Performance 1.2.4.2. HPS PLL Specifications 1.2.4.3. Quad SPI Flash Timing Characteristics 1.2.4.4. SPI Timing Characteristics 1.2.4.5. SD/MMC Timing Characteristics 1.2.4.6. USB Timing Characteristics 1.2.4.7. Ethernet Media Access Controller (EMAC) Timing Characteristics 1.2.4.8. I2C Timing Characteristics 1.2.4.9. NAND Timing Characteristics 1.2.4.10. Arm* Trace Timing Characteristics 1.2.4.11. UART Interface 1.2.4.12. GPIO Interface 1.2.4.13. HPS JTAG Timing Specifications
1.2.4.2. HPS PLL Specifications x
1.2.4.2.1. HPS PLL VCO Frequency Range 1.2.4.2.2. HPS PLL Input Clock Range 1.2.4.2.3. HPS PLL Input Jitter
1.3. Configuration Specifications x
1.3.1. POR Specifications 1.3.2. FPGA JTAG Configuration Timing 1.3.3. FPP Configuration Timing 1.3.4. Active Serial (AS) Configuration Timing 1.3.5. DCLK Frequency Specification in the AS Configuration Scheme 1.3.6. Passive Serial (PS) Configuration Timing 1.3.7. Initialization 1.3.8. Configuration Files 1.3.9. Minimum Configuration Time Estimation 1.3.10. Remote System Upgrades 1.3.11. User Watchdog Internal Oscillator Frequency Specifications
1.3.3. FPP Configuration Timing x
1.3.3.1. DCLK-to-DATA[] Ratio (r) for FPP Configuration 1.3.3.2. FPP Configuration Timing when DCLK-to-DATA[] = 1 1.3.3.3. FPP Configuration Timing when DCLK-to-DATA[] >1
1.4. I/O Timing x
1.4.1. Programmable IOE Delay 1.4.2. Programmable Output Buffer Delay
2. Arria V GZ Device Datasheet x
2.1. Electrical Characteristics 2.2. Switching Characteristics 2.3. Configuration Specification 2.4. I/O Timing 2.5. Glossary 2.6. Arria® V GZ Device Datasheet Revision History
2.1. Electrical Characteristics x
2.1.1. Operating Conditions
2.1.1. Operating Conditions x
2.1.1.1. Absolute Maximum Ratings 2.1.1.2. Maximum Allowed Overshoot and Undershoot Voltage 2.1.1.3. Recommended Operating Conditions 2.1.1.4. DC Characteristics 2.1.1.5. I/O Standard Specifications
2.1.1.3. Recommended Operating Conditions x
2.1.1.3.1. Recommended Transceiver Power Supply Operating Conditions 2.1.1.3.2. Transceiver Power Supply Requirements
2.1.1.4. DC Characteristics x
2.1.1.4.1. Supply Current 2.1.1.4.2. Power Consumption 2.1.1.4.3. I/O Pin Leakage Current 2.1.1.4.4. Bus Hold Specifications 2.1.1.4.5. On-Chip Termination (OCT) Specifications 2.1.1.4.6. Pin Capacitance 2.1.1.4.7. Hot Socketing 2.1.1.4.8. Internal Weak Pull-Up Resistor
2.2. Switching Characteristics x
2.2.1. Transceiver Performance Specifications 2.2.2. Core Performance Specifications 2.2.3. Periphery Performance
2.2.1. Transceiver Performance Specifications x
2.2.1.1. Reference Clock 2.2.1.2. Transceiver Clocks 2.2.1.3. Receiver 2.2.1.4. Transmitter 2.2.1.5. CMU PLL 2.2.1.6. ATX PLL 2.2.1.7. Fractional PLL 2.2.1.8. Clock Network Data Rate 2.2.1.9. Standard PCS Data Rate 2.2.1.10. 10G PCS Data Rate 2.2.1.11. Typical VOD Settings
2.2.2. Core Performance Specifications x
2.2.2.1. Clock Tree Specifications 2.2.2.2. PLL Specifications 2.2.2.3. DSP Block Specifications 2.2.2.4. Memory Block Specifications 2.2.2.5. Temperature Sensing Diode Specifications
2.2.3. Periphery Performance x
2.2.3.1. High-Speed I/O Specification 2.2.3.2. DLL Range Specifications 2.2.3.3. DQS Logic Block Specifications 2.2.3.4. Memory Output Clock Jitter Specifications 2.2.3.5. OCT Calibration Block Specifications 2.2.3.6. Duty Cycle Distortion (DCD) Specifications
2.2.3.1. High-Speed I/O Specification x
2.2.3.1.1. High-Speed Clock Specifications 2.2.3.1.2. Transmitter High-Speed I/O Specifications 2.2.3.1.3. Receiver High-Speed I/O Specifications 2.2.3.1.4. DPA Mode High-Speed I/O Specifications 2.2.3.1.5. Soft CDR Mode High-Speed I/O Specifications 2.2.3.1.6. Non DPA Mode High-Speed I/O Specifications
2.3. Configuration Specification x
2.3.1. POR Specifications 2.3.2. JTAG Configuration Specifications 2.3.3. Fast Passive Parallel (FPP) Configuration Timing 2.3.4. Active Serial Configuration Timing 2.3.5. Passive Serial Configuration Timing 2.3.6. Initialization 2.3.7. Configuration Files 2.3.8. Remote System Upgrades Circuitry Timing Specification 2.3.9. User Watchdog Internal Oscillator Frequency Specification
2.3.3. Fast Passive Parallel (FPP) Configuration Timing x
2.3.3.1. DCLK-to-DATA[] Ratio (r) for FPP Configuration 2.3.3.2. FPP Configuration Timing when DCLK to DATA[] = 1 2.3.3.3. FPP Configuration Timing when DCLK to DATA[] > 1
2.4. I/O Timing x
2.4.1. Programmable IOE Delay 2.4.2. Programmable Output Buffer Delay
1. Arria® V GX, GT, SX, and ST Device Datasheet
2. Arria V GZ Device Datasheet

2.2.3.1.2. Transmitter High-Speed I/O Specifications

Table 118.  Transmitter High-Speed I/O Specifications for Arria V GZ Devices

When J = 3 to 10, use the serializer/deserializer (SERDES) block.

When J = 1 or 2, bypass the SERDES block.

Symbol Conditions C3, I3L C4, I4 Unit
Min Typ Max Min Typ Max
True Differential I/O Standards - fHSDR (data rate) SERDES factor J = 3 to 10 186, 187 188 — 1250 188 — 1050 Mbps
SERDES factor J ≥ 4

LVDS TX with DPA

189, 190, 191, 192 		188 — 1600 188 — 1250 Mbps
SERDES factor J = 2, 
uses DDR Registers 188 — 193 188 — 193 Mbps
SERDES factor J = 1, 
uses SDR Register 188 — 193 188 — 193 Mbps
Emulated Differential I/O Standards with Three External Output Resistor Networks - fHSDR (data rate) 194 SERDES factor J = 4 to 10 195 188 — 840 188 — 840 Mbps
tx Jitter - True Differential I/O Standards Total Jitter for Data Rate 600 Mbps - 1.25 Gbps — — 160 — — 160 ps
Total Jitter for Data Rate < 600 Mbps — — 0.1 — — 0.1 UI
tx Jitter - Emulated Differential I/O Standards with Three External Output Resistor Network Total Jitter for Data Rate 600 Mbps - 1.25 Gbps — — 300 — — 325 ps
Total Jitter for Data Rate < 600 Mbps — — 0.2 — — 0.25 UI
tDUTY Transmitter output clock duty cycle for both True and Emulated Differential I/O Standards 45 50 55 45 50 55 %
tRISE & tFALL True Differential I/O Standards — — 200 — — 200 ps
Emulated Differential I/O Standards with three external output resistor networks — — 250 — — 300 ps
TCCS True Differential I/O Standards — — 150 — — 150 ps
Emulated Differential I/O Standards — — 300 — — 300 ps
186 If the receiver with DPA enabled and transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
187 The FMAX specification is based on the fast clock used for serial data. The interface FMAX is also dependent on the parallel clock domain which is design dependent and requires timing analysis.
188 The minimum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate.
189 Arria V GZ RX LVDS will need DPA. For Arria V GZ TX LVDS, the receiver side component must have DPA.
190 Requires package skew compensation with PCB trace length.
191 Do not mix single-ended I/O buffer within LVDS I/O bank.
192 Chip-to-chip communication only with a maximum load of 5 pF.
193 The maximum ideal data rate is the SERDES factor (J) x the PLL maximum output frequency (fOUT) provided you can close the design timing and the signal integrity simulation is clean.
194 You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin.
195 When using True LVDS RX channels for emulated LVDS TX channel, only serialization factors 1 and 2 are supported.
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