Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

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ID 683359
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide x
Device Family Support Altera PLL IP Core Parameters Functional Description Document Revision History
Altera PLL IP Core Parameters x
Altera PLL IP Core Parameters - General Tab Altera PLL IP Core Parameters - Clock Switchover Tab Altera PLL IP Core Parameters - Cascading Tab Altera PLL IP Core Parameters - MIF Streaming Tab Altera PLL IP Core Parameters - Settings Tab Altera PLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading PLL Output Counter Cascading Ports
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

Reference Clock Switchover

The reference clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature for clock redundancy, or for a dual clock domain application such as in a system. The system can turn on a redundant clock if the primary clock stops running.

Using the reference clock switchover feature, you can specify the frequency for the second input clock, and select the mode and delay for the switchover.

The clock loss detection and reference clock switchover block has the following functions:

  • Monitors the reference clock status. If the reference clock fails, the clock automatically switches to a backup clock input source. The clock updates the status of the clkbad and activeclk signals to alert the event.
  • Switches the reference clock back and forth between two different frequencies. Use the extswitch signal to manually control the switch action. After a switchover occurs, the PLL may lose lock temporarily and then regain lock.
Level Two Title