| June 2017 |
2017.06.16 |
- Added Cyclone® V SE and SX devices in adjpllin Cascading for Supported Devices table.
- Changed instances of Quartus II to Quartus Prime.
|
| May 2015 |
2015.05.04 |
- Added Arria® V and Cyclone® V devices in adjpllin Cascading for Supported Devices table.
- cclk input clock source is not supported in Cyclone V devices. Updated the information and notes in the following locations:
- Altera PLL IP Core Parameters - Cascading Tab table
- PLL-to-PLL Cascading section
- Reference Clock Inputs for Fractional PLL table
- Altera PLL Ports table
|
| August 2014 |
2014.08.01 |
- Grouped parameters in separate tables according to parameter editor tabs.
- Added parameters for the General tab and Cascading tab.
- Updated parameters for the Clock Switchover tab.
- Updated information on PLL-to-PLL Cascading.
- Added information on PLL output counter cascading.
|
| December 2013 |
1.3 |
Updated Table 3 on page 10 to update reset port information. |
| March 2013 |
1.2 |
- Added the “Reference Clock Switchover” section.
- Added the “PLL to PLL Cascading” section.
- Added new parameters for the following features: clock switchover, PLL cascading, MIF streaming, and PLL settings, in Table 1.
- Added the following new ports: refclk1, extswitch, activeclk, clkbad, cclk, adjpilin, and cascade_out, in Table 3 and Figure 3.
|
| January 2011 |
1.1 |
- Added two new parameters in Table 1.
- Updated Figure 3: ALTERA PLL Ports.
|
| July 2010 |
1.0 |
Initial release. |