Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

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ID 683359
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide x
Device Family Support Altera PLL IP Core Parameters Functional Description Document Revision History
Altera PLL IP Core Parameters x
Altera PLL IP Core Parameters - General Tab Altera PLL IP Core Parameters - Clock Switchover Tab Altera PLL IP Core Parameters - Cascading Tab Altera PLL IP Core Parameters - MIF Streaming Tab Altera PLL IP Core Parameters - Settings Tab Altera PLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading PLL Output Counter Cascading Ports
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

Altera PLL IP Core Parameters - Cascading Tab

Table 3.   Altera PLL IP Core Parameters - Cascading Tab
Parameter Legal Value Description
Create a ‘cascade out’ signal to connect with a downstream PLL Turn on or Turn off Turn on to create an output port, which indicates that this PLL will be used as a source and it connects with a destination (downstream) PLL.
Specifies which outclk to be used as cascading source Stratix® V and Arria® V: 1–18, Cyclone® V: 1–9 Specifies the cascading source.
Create an adjpllin or cclk signal to connect with an upstream PLL Turn on or Turn off Turn on to create an input port, which indicates that this PLL will be used as a destination and it connects with a source (upstream) PLL.
PLL Cascading Mode Create an adjpllin signal to connect with an upstream PLL or  Create a cclk signal to connect with an upstream PLL
  • If you select Create an adjpllin signal to connect with an upstream PLL, the adjpllin signal is created to connect with an upstream PLL during cascading.
  • If you select Create a cclk signal to connect with an upstream PLL, the cclk 5 signal is created to connect with an upstream PLL during cascading.
5 Not supported in Cyclone® V devices.
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