Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

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ID 683359
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide x
Device Family Support Altera PLL IP Core Parameters Functional Description Document Revision History
Altera PLL IP Core Parameters x
Altera PLL IP Core Parameters - General Tab Altera PLL IP Core Parameters - Clock Switchover Tab Altera PLL IP Core Parameters - Cascading Tab Altera PLL IP Core Parameters - MIF Streaming Tab Altera PLL IP Core Parameters - Settings Tab Altera PLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading PLL Output Counter Cascading Ports
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

Altera PLL IP Core Parameters - Settings Tab

Table 5.   Altera PLL IP Core Parameters - Settings Tab
Parameter Legal Value Description
PLL Auto Reset On or Off Automatically self-resets the PLL on loss of lock.
PLL Bandwidth Preset Auto, High, Low, or Medium Specifies the PLL bandwidth preset setting. The default setting is Auto.
Enable dynamic reconfiguration of PLL Turn on or Turn off Turn on to enable the dynamic reconfiguration of the PLL.
Enable access to dynamic phase shift ports Turn on or Turn off Turn on to enable the dynamic phase shift interface with the PLL.
Enable access to PLL DPA output  port Turn on or Turn off Turn on to enable the eight bits port for the eight phases of the DPA clock.
PLL DPA output division 1, 2, or 4 Specifies the PLL DPA output division value.
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