Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

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ID 683359
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide x
Device Family Support Altera PLL IP Core Parameters Functional Description Document Revision History
Altera PLL IP Core Parameters x
Altera PLL IP Core Parameters - General Tab Altera PLL IP Core Parameters - Clock Switchover Tab Altera PLL IP Core Parameters - Cascading Tab Altera PLL IP Core Parameters - MIF Streaming Tab Altera PLL IP Core Parameters - Settings Tab Altera PLL IP Core Parameters - Advanced Parameters Tab
Functional Description x
Building Blocks of a PLL PLL Lock Operation Modes Output Clocks Reference Clock Switchover PLL-to-PLL Cascading PLL Output Counter Cascading Ports
Altera Phase-Locked Loop (Altera PLL) IP Core User Guide

Altera PLL IP Core Parameters - General Tab

Table 1.   Altera PLL IP Core Parameters - General Tab
Parameter Legal Value Description
Device Speed Grade Stratix® V: 1–4, Arria® V: 3–6, Cyclone® V: 6–8 Specifies the speed grade for a device. The lower the number, the faster the speed grade.
PLL Mode Integer-N PLL or Fractional-N PLL Specifies the mode used for the Altera PLL IP core. The default mode is Integer-N PLL.
Reference Clock Frequency — Specifies the input frequency for the input clock, refclk, in MHz. The default value is 100.0 MHz. The minimum and maximum value is dependent on the selected device. The PLL reads only the numerals in the first six decimal places.
Operation Mode direct, external feedback, normal, source synchronous, zero delay buffer, or lvds Specifies the operation of the PLL. The default operation is direct mode.
  • If you select the direct mode, the PLL minimizes the length of the feedback path to produce the smallest possible jitter at the PLL output.The internal-clock and external-clock outputs of the PLL are phase-shifted with respect to the PLL clock input. In this mode, the PLL does not compensate for any clock networks.
  • If you select the normal mode, the PLL compensates for the delay of the internal clock network used by the clock output. If the PLL is also used to drive an external clock output pin, a corresponding phase shift of the signal on the output pin occurs.
  • If you select the source synchronous mode, the clock delay from pin to I/O input register matches the data delay from pin to I/O input register.
  • If you select the external feedback mode, you must connect the fbclk input port to an input pin. A board-level connection must connect both the input pin and external clock output port, fboutclk. The fbclk port is aligned with the input clock.
  • If you select the zero delay buffer mode, the PLL must feed an external clock output pin and compensate for the delay introduced by that pin. The signal observed on the pin is synchronized to the input clock. The PLL clock output connects to the altbidir port and drives zdbfbclk as an output port. If the PLL also drives the internal clock network, a corresponding phase shift of that network occurs.
  • If you select the lvds mode, the same data and clock timing relationship of the pins at the internal SERDES capture register is maintained. The mode compensates for the delays in LVDS clock network, and between the data pin and clock input pin to the SERDES capture register paths.
Enable locked output port Turn on or Turn off Turn on to enable the locked port.
Enable physical output clock parameters Turn on or Turn off Turn on to enter physical PLL counter parameters instead of specifying a desired output clock frequency.
Number of Clocks Stratix® V and Arria® V: 1–18, Cyclone® V: 1–9 Specifies the number of output clocks required for each device in the PLL design. The requested settings for output frequency, phase shift, and duty cycle are shown based on the number of clocks selected.
Desired Frequency 1 — Specifies the output clock frequency of the corresponding output clock port, outclk[], in MHz. The default value is 100.0 MHz. The minimum and maximum values depend on the device used. The PLL only reads the numerals in the first six decimal places.
Actual Frequency — Specifies the actual value for the output clock frequency.
Phase Shift units ps or degrees Specifies the phase shift unit for the corresponding output clock port, outclk[], in picoseconds (ps) or degrees.
Phase Shift — Specifies the requested value for the phase shift. The default value is 0 ps.
Actual Phase Shift — Specifies the actual value for the phase shift.
Duty Cycle 1–99 Specifies the duty cycle in percentage for the corresponding output clock port, outclk[]. The default value is 50%.
Fractional carry out 2 3 8, 16, 24, or 32 Specifies the fractional carry out (Fcout) for the Delta Sigma Modulator (DSM) mode for PLL. The fractional carry out determines the denominator in the equation K/2^Fcout.
DSM Order 2 3 1st_order, 2nd_order, 3rd_order, or disable Specifies the DSM order for shifting the fractional noise to be filtered out by the PLL to high frequencies.
Multiply Factor (M-Counter) 3 1-512 Specifies the multiply factor of M-counter.
Fractional Multiply Factor (K) 2 3 1 to (2^Fcout-1) Specifies the fractional multiply factor of DSM. Fcout is the value of fractional carry out parameter.
Divide Factor (N-Counter) 3 1-512 Specifies the divide factor of N-counter.
Make this a cascade counter 3 4 Turn on or Turn off Turn on to cascade this counter into the next counter output for larger division factor.
Divide Factor (C-Counter) 3 1-512 Specifies the divide factor for the output clock (C-counter)
1 This parameter is only available when Enable physical output clock parameters is turned off.
2 This parameter is only available in Fractional-N PLL mode.
3 This parameter is only available when Enable physical output clock parameters is turned on.
4 This feature is only supported in Quartus® Prime version 13.1 and onwards.
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