Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683532
Date 8/05/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. AFU Design 3. OPAE Support 4. Networking Interface for Open Programmable Acceleration Engine: Intel® PAC with Intel® Arria® 10 GX FPGA Revision History
1. Introduction x
1.1. How to Use this Guide
2. AFU Design x
2.1. HSSI Device Interface 2.2. Connecting the MAC to the HSSI PHY 2.3. Verifying Network Port Function
2.1. HSSI Device Interface x
2.1.1. HSSI Clocks 2.1.2. HSSI Unified Data Interface 2.1.3. HSSI PHY Control and Status 2.1.4. HSSI PR Management 2.1.5. HSSI Reset Control and Status 2.1.6. Initialization
2.2. Connecting the MAC to the HSSI PHY x
2.2.1. 4x10GBASE-SR Mode 2.2.2. 40GBASE-SR4 Mode
2.2.1. 4x10GBASE-SR Mode x
2.2.1.1. Clocks in 4x10GBASE-SR Mode 2.2.1.2. Unified Data Interface in 4x10GBASE-SR Mode 2.2.1.3. PHY Control and Status in 4x10GBASE-SR Mode 2.2.1.4. PR Management in 4x10GBASE-SR Mode 2.2.1.5. Reset Control and Status in 4x10GBASE-SR Mode 2.2.1.6. Initialization in 4x10GBASE-SR Mode 2.2.1.7. Unused 10GbE Channels
2.2.2. 40GBASE-SR4 Mode x
2.2.2.1. Clocks in 40GBASE-SR4 Mode 2.2.2.2. Unified Data Interface in 40GBASE-SR4 Mode 2.2.2.3. PHY Control and Status in 40GBASE-SR4 Mode 2.2.2.4. PR Management in 40GBASE-SR4 Mode 2.2.2.5. Reset Control and Status in 40GBASE-SR4 Mode 2.2.2.6. Initialization in 40GBASE-SR4 Mode
3. OPAE Support x
3.1. OPAE Driver HSSI sysfs Files 3.2. Managing the Network Port
3.1. OPAE Driver HSSI sysfs Files x
3.1.1. The board_id sysfs 3.1.2. The eeprom sysfs 3.1.3. The config sysfs 3.1.4. The equalizer_tune sysfs
3.1.4. The equalizer_tune sysfs x
3.1.4.1. Receiver CTLE AC Gain sysfs Encodings 3.1.4.2. Receiver VGA sysfs Encodings 3.1.4.3. Receiver CTLE DC Gain sysfs Encodings 3.1.4.4. Transmitter Pre-Emphasis First Post Tap Encodings 3.1.4.5. Transmitter Pre-Emphasis Second Post Tap Encodings 3.1.4.6. Transmitter Pre-Emphasis First Pre Tap Encodings 3.1.4.7. Transmitter Pre-Emphasis Second Pre Tap Encodings 3.1.4.8. Transmitter VOD Encodings
3.2. Managing the Network Port x
3.2.1. Configuring the Network Port 3.2.2. Reading the Base MAC Address from the Intel® PAC with Intel® Arria® 10 GX FPGA 3.2.3. Modifying HSSI PHY Transceiver PMA Settings
3.2.3. Modifying HSSI PHY Transceiver PMA Settings x
3.2.3.1. HSSI PHY Analog PMA Presets
1. Introduction
2. AFU Design
3. OPAE Support
4. Networking Interface for Open Programmable Acceleration Engine: Intel® PAC with Intel® Arria® 10 GX FPGA Revision History

3.1.4. The equalizer_tune sysfs

…/hssi_mgmt/equalizer_tune

The equalizer_tune sysfs is readable by all and writable from a privileged process (root access). It is formatted as a list of ASCII-encoded fields delimited by LF (line feed, new line) characters. Each field in the list contains a specific transceiver analog PMA setting for a specific HSSI PHY transceiver lane. There are four lanes, and each lane has a set of eight analog PMA settings. The format for each field in the list is as follows: 

<hssi-phy-transceiver-lane-index>:<analog-pma-setting-index>=<analog-pma-setting>\n

The hssi-phy-transceiver-lane-index subfield specifies the HSSI PHY transceiver lane number as shown in the table below.

Table 12.  HSSI PHY Transceiver Lane Index Subfield
Supported Range of ASCII-Encoded String Values Description
"0" HSSI PHY transceiver lane 0
"1" HSSI PHY transceiver lane 1
"2" HSSI PHY transceiver lane 2
"3" HSSI PHY transceiver lane 3

The analog-pma-setting-index subfield specifies a transceiver analog PMA setting, or group of settings, for the HSSI PHY lane indicated by the hssi-phy-transceiver-lane-index subfield as shown in the table below.

Table 13.   HSSI PHY Transceiver Analog PMA Setting Index Subfield
Supported Range of ASCII-Encoded String Values Description Reference in Intel Arria 10 Transceiver PHY User Guide
"0" Receiver High Gain Mode Equalizer AC Gain Control (CTLE ACGAIN) Table Available Options in XCVR_A10_RX_ADP_CTLE_ACGAIN_4S
"1" Receiver Variable Gain Amplifier Voltage Swing Select (VGA) Table Available Options in XCVR_A10_RX_ADP_VGA_SEL
"2" Receiver High Gain Mode Equalizer DC Gain Control (CTLE DCGAIN) Table Available Options in XCVR_A10_RX_EQ_DC_GAIN_TRIM
"3" Transmitter Pre-Emphasis First Post-Tap Magnitude Table Available Options in XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP
"4" Transmitter Pre-Emphasis Second Post-Tap Magnitude Table Available Options in XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
"5" Transmitter Pre-Emphasis First Pre-Tap Magnitude Table Available Options in XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T
"6" Transmitter Pre-Emphasis Second Pre-Tap Magnitude Table Available Options in XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T
"7" Transmitter Output Swing Level Table Available Options in XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL

The ASCII-encoded string value specified by the analog-pma-setting subfield corresponds to the encoded value for the HSSI PHY transceiver analog PMA setting on the lane indicated by the hssi-phy-transceiver-lane-index:analog-pma-setting-index subfields.

The equalizer_tune sysfs reads and configures analog PMA setting value encodings for the analog-pma-setting subfield. For descriptions of those setting value encodings, refer to the Encodings sections that follow.


Section Content
Receiver CTLE AC Gain sysfs Encodings
Receiver VGA sysfs Encodings
Receiver CTLE DC Gain sysfs Encodings
Transmitter Pre-Emphasis First Post Tap Encodings
Transmitter Pre-Emphasis Second Post Tap Encodings
Transmitter Pre-Emphasis First Pre Tap Encodings
Transmitter Pre-Emphasis Second Pre Tap Encodings
Transmitter VOD Encodings

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