Arria® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683213
Date 10/18/2023
Public
Document Table of Contents

1.3. Logic Array Blocks and Adaptive Logic Modules in Arria V Devices Revision History

Date Version Changes
December 2016 2016.12.09 Added description on clock source in the LAB Control Signals section.
December 2015 2015.12.21 Changed instances of Quartus II to Quartus Prime.
January 2014 2014.01.10 Added multiplexers for the bypass paths and register outputs in the following diagrams:
  • ALM High-Level Block Diagram for Arria® V GX, GT, SX, and ST Devices
  • ALM High-Level Block Diagram for Arria® V GZ Devices
  • Template for Supported 7-Input Functions in Extended LUT Mode for Arria® V Devices
  • ALM in Arithmetic Mode for Arria® V Devices
  • ALM in Shared Arithmetic Mode for Arria® V Devices
May 2013 2013.05.06
  • Added link to the known document issues in the Knowledge Base.
  • Updated local and direct link interconnects section to add M20K memory block.
  • Removed register chain outputs information in ALM output section.
  • Removed reg_chain_in and reg_chain_out ports in ALM high-level block diagram and ALM connection details diagram for Arria® V GX, GT, SX, and ST devices.
November 2012 2012.11.19
  • Added MLAB structure for Arria® V GZ devices.
  • Added LAB-wide control signals diagram for Arria® V GZ devices.
  • Added ALM high level block diagram for Arria® V GZ devices.
  • Added ALM connection details diagram for Arria® V GZ devices.
  • Reorganized content and updated template.
June 2012 2.0

Updated for the Quartus II software v12.0 release:

  • Restructured chapter.
  • Updated Figure 1–6.
November 2011 1.1 Restructured chapter.
May 2011 1.0 Initial release.