LVDS SERDES Transmitter / Receiver IP Cores User Guide

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ID 683062
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide x
1.1. Features 1.2. Parameter Settings 1.3. Ports 1.4. Prototypes and Component Declarations 1.5. Functional Description 1.6. Simulating Intel® FPGA IP Cores 1.7. Generating ALTLVDS IP Core Using Clear Box Generator 1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives 1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.1. Features x
1.1.1. Resource Utilization and Performance
1.2. Parameter Settings x
1.2.1. ALTLVDS_TX Parameter Settings 1.2.2. ALTLVDS_RX Parameter Settings 1.2.3. Command Line Interface Parameters
1.3. Ports x
1.3.1. ALTLVDS_TX Ports 1.3.2. ALTLVDS_RX Ports
1.4. Prototypes and Component Declarations x
1.4.1. Verilog HDL Prototype 1.4.2. VHDL Component Declaration 1.4.3. VHDL LIBRARY-USE Declaration
1.5. Functional Description x
1.5.1. Receiver Modes 1.5.2. DPA PLL Calibration 1.5.3. Initialization and Reset 1.5.4. Source-Synchronous Timing Analysis and Timing Constraints 1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel 1.5.6. ALTLVDS IP Core in External PLL Mode
1.5.1. Receiver Modes x
1.5.1.1. DPA Mode 1.5.1.2. Non-DPA Mode 1.5.1.3. Soft-CDR Mode
1.5.1.3. Soft-CDR Mode x
1.5.1.3.1. Clock Forwarding 1.5.1.3.2. Standard Mode 1.5.1.3.3. No Output Register Mode
1.5.2. DPA PLL Calibration x
1.5.2.1. DPA PLL Calibration in Stratix IV ES Devices 1.5.2.2. DPA PLL Calibration in Arria II and Stratix IV Devices and Later 1.5.2.3. Effects of DPA PLL Calibration
1.5.3. Initialization and Reset x
1.5.3.1. Initializing ALTLVDS_TX and ALTLVDS_RX 1.5.3.2. Resetting the DPA 1.5.3.3. Aligning the Word Boundaries 1.5.3.4. Recommended Initialization and Reset Flow
1.5.4. Source-Synchronous Timing Analysis and Timing Constraints x
1.5.4.1. Dedicated SERDES 1.5.4.2. SERDES in LEs 1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew 1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI 1.5.4.5. Setting Timing Constraints Manually in the Synopsys Design Constraint File
1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew x
1.5.4.3.1. Obtaining the RSKM Report 1.5.4.3.2. Obtaining the TCCS Report
1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI x
1.5.4.4.1. Constraining the Input Clock Signal
1.5.6. ALTLVDS IP Core in External PLL Mode x
1.5.6.1. PLL Clock Signals for LVDS Interface in External PLL Mode 1.5.6.2. External PLL Compensation Mode for ALTLVDS IP Core in External PLL Mode
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide

1.3.2. ALTLVDS_RX Ports

The following table lists the input and output ports for the ALTLVDS_RX IP core.

Note: n is the number of channels. m is the deserialization_factor × number_of_channels.
Table 10.   ALTLVDS_RX Input and Output Ports For Stratix® IV, Arria® II, Cyclone® IV, and Intel® Cyclone® 10 LP devices, use the ALTPLL IP core. For Stratix® V, Arria® V, and Cyclone® V devices use the Altera PLL IP core.
Port Name Direction Width (Bit) Description
dpa_pll_recal Input 1 Enables dynamic recalibration without resetting the DPA circuitry or the PLL. Only available in DPA mode when PLL calibration is enabled.
pll_areset Input 1 Asynchronously resets all counters to initial values. The minimum pulse width requirement for this signal is 10 ns.
pll_phasedone Input 1 Specifies whether dynamic phase reconfiguration is complete. Only available when using an external PLL when PLL calibration is enabled.
rx_cda_reset Input n

Asynchronous reset to the data realignment circuitry. The minimum pulse width requirement for this reset is one parallel clock cycle. This signal resets the data realignment block.

This port is not available for Arria® V and Cyclone® V devices. You can reset the CDA or bitslip in Arria® V and Cyclone® V devices by asserting the rx_channel_data_align signal until the bitslip counter rolls over.

rx_channel_data_align Input n Controls byte alignment circuitry.
rx_coreclk Input n LVDS reference input clock. Replaces the non-peripheral clock from the PLL. One clock for each channel.
rx_data_align Input 1 Controls byte alignment circuitry. You can register this port using the rx_outclock port. This port is available when implement_in_les parameter is set to ON and can be implemented using flexible LVDS.
rx_data_align_reset Input 1 Resets the byte alignment circuitry. Use the rx_data_align_reset input port when you need to reset the PLL during device operation and when you need to re-establish the word alignment. This port is available when implement_in_les parameter is set to ON.
rx_data_reset Input n Asynchronous reset for all channels, excluding the PLL.
rx_deskew Input 1 Specifies whether to activate calibration mode.
rx_dpa_lock_reset Input n Forces the rx_dpa_locked port to low and forces the lock counter to start counting again.
rx_dpll_enable Input n Enables the data path that flows through the DPA circuit. This port is available only when DPA mode is enabled. This port is supported in Arria GX, HardCopy® II, Stratix II, and Stratix II GX devices only.
rx_dpll_hold Input n Prevents the DPA circuitry from switching to a new phase. When low, the DPA tracks any dynamic phase variations between the clock and data. When high, the DPA holds the last locked phase and does not track any dynamic phase variations between the clock and data. This port is not available in non-DPA mode.
rx_dpll_reset Input n Asynchronous reset for all channels.
rx_enable Input 1 Enables external PLL usage. When the rx_enable port is specified, it must connect to the enable0 or enable1 port of a PLL IP core instance configured in LVDS mode. However, the enable0, enable1 ports and the Set up PLL in LVDS mode option are available for Stratix II devices only.
rx_fifo_reset Input n Asynchronous reset to the FIFO between the DPA and the data realignment circuits. The synchronizer block must be reset after a DPA loses lock condition and the data checker shows corrupted received data. The minimum pulse width requirement for this reset is one parallel clock cycle. This signal resets the FIFO block. Only available when DPA mode is enabled.
rx_in[] Input n LVDS serial data input port of n channels wide. rx_in[(n-1)..0] is deserialized and driven on rx_out[(J * n)-1 ..0] where J is the deserialization factor and n is the number of channels. rx_in[0] drives data to rx_out[(J-1)..0]. rx_in[1] drives data to the next J number of bits on rx_out.
rx_inclock Input 1 LVDS reference input clock. The parameter editor automatically selects the appropriate PLL multiplication factor based on the data rate and reference clock frequency selection. When using Stratix II devices in external PLL mode, connect the rx_inclock port to the sclkout0 or sclkout1 port. When using Cyclone® and Cyclone® II devices in external PLL mode, connect the rx_inclock port to other clocks. Refer to the respective device handbook for supported input clock frequency ranges.
rx_pll_enable Input 1 Enables control for the LVDS PLL.
rx_readclock Input 1 Clock input port for reading operation.
rx_reset Input n Asynchronous reset to the DPA circuitry and FIFO. The minimum pulse width requirement for this reset is one parallel clock cycle. This signal resets DPA and FIFO blocks. You can connect this port if the enable_dpa_mode parameter is turned on.
rx_syncclock Input 1 Slow clock input port.
dpa_pll_cal_busy Output 1 Busy signal that is asserted high when PLL calibration occurs. PLL clock signals are phase adjusted for two fast clock cycles ahead. Available only when DPA mode with PLL calibration is enabled.
pll_phasecounterselect Output 1 Specifies the PLL counter select. Available only when DPA mode with PLL calibration is enabled.
pll_phasestep Output 1 Specifies dynamic phase shifting. Available only when DPA mode with PLL calibration is enabled.
pll_phaseupdown Output 1 Specifies dynamic phase adjustment. Available only when DPA mode with PLL calibration is enabled.
pll_scanclk Output 1 Clock signal for the serial scan chain. Available only when DPA mode with PLL calibration is enabled.
rx_cda_max Output n Data re-alignment (bit slip) roll-over signal. When high for one parallel clock cycle, this signal indicates that the user-programmed number of bits for the word boundary to roll-over have been slipped. Indicates when the next rx_channel_data_align pulse restores the serial data latency back to 0.
rx_divfwdclk Output n Parallel DPA clock to the FPGA fabric logic array. The parallel receiver output data to the FPGA fabric logic array is synchronous to this clock in soft-CDR mode. This signal is not available in non-DPA and DPA modes. Divides and forwards the clock to the source from the DPA block of the clock channel. When the enable_soft_cdr_mode parameter is set to ON, the rx_divfwdclk port is used. When set to ON, the rx_divfwdclk port clocks the synchronization registers.
rx_dpa_locked Output n Indicates whether the channel is locked to DPA mode. This signal only indicates an initial DPA lock condition to the optimum phase after power up or reset. This signal is not deasserted if the DPA selects a new phase out of the eight clock phases to sample the received data. You must not use the rx_dpa_locked signal to determine a DPA loss-of-lock condition.
rx_locked Output 1 Provides the LVDS PLL status. Stays high when the PLL is locked to rx_inclock, and stays low when the PLL fails to lock.
rx_out Output m Receiver parallel data output. The data bus width per channel is the same as the deserialization factor (DF). The output data is synchronous to the rx_outclock signal in non-DPA and DPA modes. It is synchronous to the rx_divfwdclk signal in soft-CDR mode.
rx_outclock Output 1 Parallel output clock from the receiver PLL. The parallel data output from the receiver is synchronous to this clock in non-DPA and DPA modes. This port is not available when you turn on the Use External PLL option in the parameter editor. The FPGA fabric-receiver interface clock must be driven by the PLL instantiated through the PLL IP core parameter editor.
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