LVDS SERDES Transmitter / Receiver IP Cores User Guide

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ID 683062
Date 12/15/2017
Public
Document Table of Contents
Document Table of Contents x
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide x
1.1. Features 1.2. Parameter Settings 1.3. Ports 1.4. Prototypes and Component Declarations 1.5. Functional Description 1.6. Simulating Intel® FPGA IP Cores 1.7. Generating ALTLVDS IP Core Using Clear Box Generator 1.8. LVDS SERDES Transmitter/Receiver IP Cores User Guide Archives 1.9. Document Revision History for LVDS SERDES Transmitter/Receiver IP Cores User Guide
1.1. Features x
1.1.1. Resource Utilization and Performance
1.2. Parameter Settings x
1.2.1. ALTLVDS_TX Parameter Settings 1.2.2. ALTLVDS_RX Parameter Settings 1.2.3. Command Line Interface Parameters
1.3. Ports x
1.3.1. ALTLVDS_TX Ports 1.3.2. ALTLVDS_RX Ports
1.4. Prototypes and Component Declarations x
1.4.1. Verilog HDL Prototype 1.4.2. VHDL Component Declaration 1.4.3. VHDL LIBRARY-USE Declaration
1.5. Functional Description x
1.5.1. Receiver Modes 1.5.2. DPA PLL Calibration 1.5.3. Initialization and Reset 1.5.4. Source-Synchronous Timing Analysis and Timing Constraints 1.5.5. Arria II GX, Arria® V, Arria® V GZ, Cyclone® V, and Stratix® V LVDS Package Skew Compensation Report Panel 1.5.6. ALTLVDS IP Core in External PLL Mode
1.5.1. Receiver Modes x
1.5.1.1. DPA Mode 1.5.1.2. Non-DPA Mode 1.5.1.3. Soft-CDR Mode
1.5.1.3. Soft-CDR Mode x
1.5.1.3.1. Clock Forwarding 1.5.1.3.2. Standard Mode 1.5.1.3.3. No Output Register Mode
1.5.2. DPA PLL Calibration x
1.5.2.1. DPA PLL Calibration in Stratix IV ES Devices 1.5.2.2. DPA PLL Calibration in Arria II and Stratix IV Devices and Later 1.5.2.3. Effects of DPA PLL Calibration
1.5.3. Initialization and Reset x
1.5.3.1. Initializing ALTLVDS_TX and ALTLVDS_RX 1.5.3.2. Resetting the DPA 1.5.3.3. Aligning the Word Boundaries 1.5.3.4. Recommended Initialization and Reset Flow
1.5.4. Source-Synchronous Timing Analysis and Timing Constraints x
1.5.4.1. Dedicated SERDES 1.5.4.2. SERDES in LEs 1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew 1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI 1.5.4.5. Setting Timing Constraints Manually in the Synopsys Design Constraint File
1.5.4.3. Receiver Skew Margin and Transmitter Channel-to-Channel Skew x
1.5.4.3.1. Obtaining the RSKM Report 1.5.4.3.2. Obtaining the TCCS Report
1.5.4.4. Setting Timing Constraints Using the TimeQuest Timing Analyzer GUI x
1.5.4.4.1. Constraining the Input Clock Signal
1.5.6. ALTLVDS IP Core in External PLL Mode x
1.5.6.1. PLL Clock Signals for LVDS Interface in External PLL Mode 1.5.6.2. External PLL Compensation Mode for ALTLVDS IP Core in External PLL Mode
1. LVDS SERDES Transmitter/Receiver IP Cores User Guide

1.3.1. ALTLVDS_TX Ports

The following table lists the input and output ports for the ALTLVDS_TX IP core.

n is the number of channels. m is the deserialization_factor × number_of_channels.

Note: If you use dedicated SERDES, regardless of device family, you do not need to make additional constraints on the data port.
Table 9.   ALTLVDS_TX Input and Output Ports For Stratix® IV, Arria® II, Cyclone® IV, and Intel® Cyclone® 10 LP devices, use the ALTPLL IP core. For Stratix® V, Arria® V, and Cyclone® V devices use the Altera PLL IP core.

Port Name

Direction

Width (Bit)

Description

pll_areset

Input

1

Asynchronously resets all counters to the initial values.

sync_inclock

Input

1

Optional clock for the input registers.

tx_data_reset

Input

n

Asynchronous reset for the shift registers, capture registers, and synchronization registers for all channels. This port is available only when implement_in_les parameter is set to ON. This port does not affect the data realignment block or the PLL.

tx_enable

Input

1

Enables external PLL usage.

When the tx_enable port is specified, connect the port to the enable0 or enable1 port of a PLL IP core instance.

However, the enable0, enable1 ports and the Set up PLL in LVDS mode option are available for Stratix II devices only.

tx_in[]

Input

m

This is parallel data which needs to be serially transmitted by the IP core. Input data must be synchronous to the tx_coreclock signal. The data bus width per channel is the same as the serialization factor (SF)

tx_inclock

Input

1

Reference clock input for the transmitter PLL.

The parameter editor automatically selects the appropriate PLL multiplication factor based on the data rate and reference clock frequency selection.

When using Stratix II devices in external PLL mode, connect the tx_inclock port to the sclkout0 or sclkout1 port. When using Cyclone® and Cyclone® II devices in external PLL mode, connect the tx_inclock port to other clocks.

Refer to the respective device handbook for supported input clock frequency ranges.

tx_pll_enable

Input

1

Enables control for the LVDS PLL.

tx_syncclock

Input

1

Slow clock input port.

In the Intel® Quartus® Prime software version 8.0 or later, the tx_syncclock port is necessary for even deserialization factors in external PLL mode.

tx_coreclock

Output

1

Output clock used to feed non-peripheral logic. FPGA fabric-transmitter interface clock. The parallel transmitter data generated in the FPGA fabric must be clocked with this clock.

tx_locked

Output

1

Provides the LVDS PLL status.

This port stays high when the PLL is locked to the input reference clock, and stays low when the PLL fails to lock.

tx_out[]

Output

n

Serialized LVDS data output port of n channels wide.

tx_out[(n-1)..0] drives parallel data from tx_in[(J * n)-1 ..0] where J is the serialization factor and n is the number of channels. tx_out[0] drives data from tx_in[(J-1)..0]. tx_out[1] drives data from the next J number of bits on tx_in.

tx_outclock

Output

1

External reference clock.

The frequency of this clock is programmable to be the same as the data rate (up to 717 MHz), half the data rate, or one-fourth the data rate. The phase offset of this clock, with respect to the serial data, is programmable in increments of 45°.

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