AN 825: Partially Reconfiguring a Design: on Intel® Stratix® 10 GX FPGA Development Board

Download PDF
ID 683880
Date 12/07/2020
Public
Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board
Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for AN 825: Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Defining Personas Step 5: Creating Revisions Step 6: Compiling the Base Revision Step 7: Preparing PR Implementation Revisions Step 8: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 5: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 8: Programming the Board x
Troubleshooting PR Programming Errors
Partially Reconfiguring a Design on Intel® Stratix® 10 GX FPGA Development Board

Setting the Base Revision Type

  1. Click Project > Revisions.
  2. In Revision Name, select the blinking_led revision, and then click Set Current.
  3. Click Apply. The blinking_led revision displays as the current revision.
  4. To set the Revision Type for blinking_led, click Assignments > Settings > General.
  5. For Revision Type, select Partial Reconfiguration - Base, and then click OK.
  6. Verify that the blinking_led.qsf now contains the following assignment: 
    
##blinking_led.qsf
set_global_assignment -name REVISION_TYPE PR_BASE
Level Two Title