ALTIOBUF IP Core User Guide

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ID 683471
Date 1/13/2020
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Document Table of Contents
Document Table of Contents x
ALTIOBUF IP Core User Guide
ALTIOBUF IP Core User Guide x
Device Family Support ALTIOBUF Features I/O Buffer and Dynamic Delay Integration ALTIOBUF Common Application ALTIOBUF Parameters ALTIOBUF Functional Description ALTIOBUF References ALTIOBUF IP Core User Guide Archives Document Revision History for the ALTIOBUF IP Core User Guide
ALTIOBUF Parameters x
Using the Port and Parameter Definitions
ALTIOBUF Functional Description x
ALTIOBUF Input, Output, and OE Paths
ALTIOBUF Input, Output, and OE Paths x
ALTIOBUF Input Buffer ALTIOBUF Output Buffer ALTIOBUF Bidirectional Buffer Dynamic Delay Chain Valid Values Assignments Necessary For Dynamic Delay Chain Usage
ALTIOBUF Input Buffer x
Differential Mode Pin Naming Convention
ALTIOBUF References x
ALTIOBUF Signals and Parameters: As Input Buffer ALTIOBUF Signals and Parameters: As Output Buffer ALTIOBUF Signals and Parameters: As Bidirectional Buffer Verilog HDL Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration
ALTIOBUF IP Core User Guide

ALTIOBUF Signals and Parameters: As Bidirectional Buffer

Table 12.   ALTIOBUF (As Bidirectional Buffer) Input PortsThis table lists the input ports for the ALTIOBUF IP core (as bidirectional buffer).
Name Required Description
datain[] Yes The input buffer input port. Input port [NUMBER_OF_CHANNELS - 1..0] wide. The input signal to the I/O output buffer element.
io_config_datain No Input port that feeds the datain port of IO_CONFIG for user-driven dynamic delay chain. Input port used to feed input data to the serial load shift register. The value is a 1-bit wire shared among all I/O instances.

This port is available only if the USE_IN_DYNAMIC_DELAY_CHAIN, USE_OUT_DYNAMIC_DELAY_CHAIN1, or USE_OUT_DYNAMIC_DELAY_CHAIN2 parameter value is TRUE.

io_config_clk No Input clock port that feeds the IO_CONFIG for user-driven dynamic delay chain. The maximum frequency for this clock is 30 MHz. Input port used as the clock signal of shift register block. The value is a 1-bit wire shared among all I/O instances.

This port is available only if the USE_IN_DYNAMIC_DELAY_CHAIN, USE_OUT_DYNAMIC_DELAY_CHAIN1, or USE_OUT_DYNAMIC_DELAY_CHAIN2 parameter value is TRUE.

io_config_clkena[] No Input clock-enable that feeds the ena port of IO_CONFIG for user-driven dynamic delay chain. Input port [NUMBER_OF_CHANNELS - 1..0] wide. Input port used as the clock signal of the shift register block.

This port is available only if the USE_IN_DYNAMIC_DELAY_CHAIN, USE_OUT_DYNAMIC_DELAY_CHAIN1, or USE_OUT_DYNAMIC_DELAY_CHAIN2 parameter value is TRUE.

io_config_update No Input port that feeds the IO_CONFIG update port for user-driven dynamic delay chain. When asserted, the serial load shift register bits feed the parallel load register. The value is a 1-bit wire shared among all I/O instances.

This port is available only if the USE_IN_DYNAMIC_DELAY_CHAIN, USE_OUT_DYNAMIC_DELAY_CHAIN1, or USE_OUT_DYNAMIC_DELAY_CHAIN2 parameter value is TRUE.

oe[] Yes The output-enable source to the tri-state buffer. Input port [NUMBER_OF_CHANNELS - 1..0] wide. If omitted, the default is VCC.
oe_b No The output-enable source to the tri-state buffer. Input port [NUMBER_OF_CHANNELS - 1..0] wide. If omitted, the default is VCC. Port is available only when the USE_DIFFERENTIAL_MODE parameter value is TRUE.
dynamicterminationcontrol[] No Input signal for bidirectional I/Os. Input port [NUMBER_OF_CHANNELS - 1..0] wide. When specified, this port selects from the core either Rs code, when the input value is LOW; or Rt code, when the input value is HIGH. Enable Rt only when the bidirectional I/O is receiving input. When the bidirectional I/O is not receiving input, disable this port for optimal output performance and power dissipation.
Value Rs Code Rt Code
0 1 0
1 0 1
dynamicterminationcontrol_b No Input signal for bidirectional I/Os. Input port [NUMBER_OF_CHANNELS - 1..0] wide. When specified, this port selects from the core either Rs code, when the input value is LOW; or Rt code, when the input value is HIGH. Enable Rt only when the bidirectional I/O is receiving input. When the bidirectional I/O is not receiving input, disable this port for optimal output performance and power dissipation. Port is available only when the USE_DIFFERENTIAL_MODE parameter value is TRUE.
Value Rs Code Rt Code
0 1 0
1 0 1
seriesterminationcontrol[] No Receives the current state of the pull up and pull down Rs control buses from a termination logic block. [WIDTH_STC * NUMBER_OF_CHANNELS - 1..0] wide. Port is applicable only when the USE_TERMINATION_CONTROL parameter value is TRUE.
seriesterminationcontrol_b No Receives the current state of the pull up and pull down Rs control buses from a termination logic block. [WIDTH_STC * NUMBER_OF_CHANNELS - 1..0] wide. Port is applicable only when the USE_TERMINATION_CONTROL parameter value is TRUE.
parallelterminationcontrol[] No Receives the current state of the pull up and pull down Rt control buses from a termination logic block. Input port [((WIDTH_PTC * NUMBER_OF_CHANNELS) - 1)..0] wide. Port is applicable only when the USE_TERMINATION_CONTROL parameter value is TRUE.
parallelterminationcontrol_b No Receives the current state of the pull up and pull down Rt control buses from a termination logic block. Input port [((WIDTH_PTC * NUMBER_OF_CHANNELS) - 1)..0] wide. Port is applicable only when the USE_TERMINATION_CONTROL parameter value is TRUE.
Table 13.   ALTIOBUF (As Bidirectional Buffer) Output PortsThis table lists the output ports for ALTIOBUF IP core (as bidirectional buffer)
Name Required Description
dataout[] Yes Buffer output port. Output port [NUMBER_OF_CHANNELS - 1..0] wide. The I/O output buffer element output.
Table 14.   ALTIOBUF (As Bidirectional Buffer) Bidirectional PortsThis table lists the bidirectional ports for ALTIOBUF IP core (as bidirectional buffer)
Name Required Description
dataio[] Yes Bidirectional port that directly feeds a bidirectional pin in the top-level design. Bidirectional port [(NUMBER_OF_CHANNELS - 1)..0] wide.
dataio_b[] No Bidirectional DDR port that directly feeds a bidirectional pin in the top-level design. Bidirectional port [(NUMBER_OF_CHANNELS - 1)..0] wide. The negative signal input/output to/from the I/O buffer. This port is used only if the use_differential_mode_parameter is set to TRUE.
Table 15.   ALTIOBUF (As Bidirectional Buffer) ParameterThis table lists the parameters for ALTIOBUF IP core (as bidirectional buffer)
Name Required Type Description
ENABLE_BUS_HOLD No String Specifies whether the bus hold circuitry is enabled. Values are TRUE and FALSE. When set to TRUE, bus hold circuitry is enabled, and the previous value, instead of high impedance, is assigned to the output port when there is no valid input. If omitted, the default is FALSE.

Currently, ENABLE_BUS_HOLD and USE_DIFFERENTIAL_MODE cannot be used simultaneously.

USE_ DIFFERENTIAL_MODE No String Specifies whether the bidirectional buffer is differential. Values are TRUE and FALSE. When set to TRUE, the output is the difference between the dataio and dataio_b ports. If omitted, the default is FALSE.

Currently, ENABLE_BUS_HOLD and USE_DIFFERENTIAL_MODE cannot be used simultaneously.

OPEN_DRAIN_OUTPUT No String Open drain mode. Values are TRUE and FALSE. If omitted, the default is FALSE. OPEN_DRAIN_OUTPUT and USE_DIFFERENTIAL_MODE cannot be used simultaneously.
USE_TERMINATION_CONTROL No String Specifies series termination control and parallel termination control. Values are TRUE and FALSE. If omitted, the default is FALSE. When this parameter is used for Arria® II GX devices and Cyclone® series, only series termination control is available. Stratix® series supports both.
USE_DYNAMIC_TERMINATION_CONTROL No String Specifies dynamic termination control. Values are TRUE and FALSE. If omitted, the default is FALSE. An error is issued if parallel termination (Rt) is on and dynamic termination control is not connected on a bidir pin. An error is issued if Rt is off and dynamic termination control is connected on an input or bidirectional pin.
USE_IN_DYNAMIC_DELAY_CHAIN No String Specifies whether the input buffer incorporates the user-driven dynamic delay chain in the IP core, specifically, IO_CONFIG and an input delay cell. Additional input ports are io_config_clk, io_config_clkena, io_config_update, and io_config_datain. Values are TRUE and FALSE. If omitted, the default is FALSE.
USE_OUT_DYNAMIC_DELAY_CHAIN1 No String Specifies whether the output buffer incorporates a user-driven dynamic delay chain in the IP core, specifically, IO_CONFIG and the first output delay cell. Additional input ports are io_config_clk, io_config_clkena, io_config_update, and io_config_datain. Values are TRUE and FALSE. If omitted, the default is FALSE.
USE_OUT_DYNAMIC_DELAY_CHAIN2 No String Specifies whether the output buffer incorporates a user-driven dynamic delay chain in the IP core, specifically, IO_CONFIG and the second output delay cell. Additional input ports are io_config_clk, io_config_clkena, io_config_update, and io_config_datain. Values are TRUE and FALSE. If omitted, the default is FALSE.
NUMBER_OF_CHANNELS Yes Integer Specifies the number of I/O buffers that must be instantiated. Value must be greater than or equal to 1. A value of 1 indicates that the buffer is a 1-bit port and accommodates wires. A value greater than 1 indicates that the port can be connected to a bus of width NUMBER_OF_CHANNELS.
WIDTH_STC No Integer Specifies the width setting for the series termination control bus.
WIDTH_PTC No Integer Specifies the width setting for the parallel termination control bus.
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