ALTIOBUF IP Core User Guide

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ID 683471
Date 1/13/2020
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Document Table of Contents
Document Table of Contents x
ALTIOBUF IP Core User Guide
ALTIOBUF IP Core User Guide x
Device Family Support ALTIOBUF Features I/O Buffer and Dynamic Delay Integration ALTIOBUF Common Application ALTIOBUF Parameters ALTIOBUF Functional Description ALTIOBUF References ALTIOBUF IP Core User Guide Archives Document Revision History for the ALTIOBUF IP Core User Guide
ALTIOBUF Parameters x
Using the Port and Parameter Definitions
ALTIOBUF Functional Description x
ALTIOBUF Input, Output, and OE Paths
ALTIOBUF Input, Output, and OE Paths x
ALTIOBUF Input Buffer ALTIOBUF Output Buffer ALTIOBUF Bidirectional Buffer Dynamic Delay Chain Valid Values Assignments Necessary For Dynamic Delay Chain Usage
ALTIOBUF Input Buffer x
Differential Mode Pin Naming Convention
ALTIOBUF References x
ALTIOBUF Signals and Parameters: As Input Buffer ALTIOBUF Signals and Parameters: As Output Buffer ALTIOBUF Signals and Parameters: As Bidirectional Buffer Verilog HDL Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration
ALTIOBUF IP Core User Guide

Assignments Necessary For Dynamic Delay Chain Usage

If you utilize the dynamic delay chain for the I/O buffer IP core, a MEMORY_INTERFACE_DATA_PIN_GROUP assignment to the I/O buffer block is necessary to enable it to go through fitting.

This is because the IP core utilizes the IO_CONFIG and DELAY_CHAIN blocks that are associated with the use of DDR interfaces. Therefore, the Intel® Quartus® Prime Fitter requires the assignment to determine the placement of the blocks with the respective IO_xBUF block.

The format of the MEMORY_INTERFACE_DATA_PIN assignments generally appears as the following:

MEMORY_INTERFACE_DATA_PIN_GROUP {4|9|18|36} -from iobuf[0] -to iobuf[0]
MEMORY_INTERFACE_DATA_PIN_GROUP {4|9|18|36} -from iobuf[0] -to iobuf[1]
MEMORY_INTERFACE_DATA_PIN_GROUP {4|9|18|36} -from iobuf[0] -to iobuf[2]
….
MEMORY_INTERFACE_DATA_PIN_GROUP {4|9|18|36} -from iobuf[0] -to iobuf[n]

iobuf is the name of the buffer, either a stratixiii_io_obuf (for the output buffer) or stratixiii_io_ibuf (for the input buffer). For the bidirectional buffer, either one is acceptable.

Figure 9. Output BufferThis figure shows an example of an output buffer.

To allow this particular design to be fit, add the following line in the Intel® Quartus® Prime Setting File (.qsf): 

set_instance_assignment -name MEMORY_INTERFACE_DATA_PIN_GROUP 4 -from "u2|test_output_iobuffer_iobuf_out_kk21:test_output_iobuffer_iobuf_out_kk21_component|obufa_0" -to "u2|test_output_iobuffer_iobuf_out_kk21:test_output_iobuffer_iobuf_out_kk21_component|obufa_0"

You can also use the Assignment Editor to set the column fields as shown in the following table:

Table 4.  Assigning the MEMORY_INTERFACE_DATA_PIN_GROUP Assignment
Column Setting
From u2|test_output_iobuffer_iobuf_out_kk21:test_output_iobuffer_iobuf_out_kk21_component|obufa_0
To u2|test_output_iobuffer_iobuf_out_kk21:test_output_iobuffer_iobuf_out_kk21_component|obufa_0
Assignment Name MEMORY_INTERFACE_DATA_PIN_GROUP
Value 4
Enable Yes

Then, set the Value field as shown in the following table:

Table 5.  MEMORY_INTERFACE_DATA_PIN_GROUP Value
Number of Channels MEMORY_INTERFACE_DATA_PIN_GROUP Value
1–6 4
7–12 9
13–24 18
25–48 36

The design example associated with this user guide has this assignment.

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