ALTIOBUF IP Core User Guide

Download PDF
ID 683471
Date 1/13/2020
Public
Document Table of Contents
Document Table of Contents x
ALTIOBUF IP Core User Guide
ALTIOBUF IP Core User Guide x
Device Family Support ALTIOBUF Features I/O Buffer and Dynamic Delay Integration ALTIOBUF Common Application ALTIOBUF Parameters ALTIOBUF Functional Description ALTIOBUF References ALTIOBUF IP Core User Guide Archives Document Revision History for the ALTIOBUF IP Core User Guide
ALTIOBUF Parameters x
Using the Port and Parameter Definitions
ALTIOBUF Functional Description x
ALTIOBUF Input, Output, and OE Paths
ALTIOBUF Input, Output, and OE Paths x
ALTIOBUF Input Buffer ALTIOBUF Output Buffer ALTIOBUF Bidirectional Buffer Dynamic Delay Chain Valid Values Assignments Necessary For Dynamic Delay Chain Usage
ALTIOBUF Input Buffer x
Differential Mode Pin Naming Convention
ALTIOBUF References x
ALTIOBUF Signals and Parameters: As Input Buffer ALTIOBUF Signals and Parameters: As Output Buffer ALTIOBUF Signals and Parameters: As Bidirectional Buffer Verilog HDL Prototype VHDL Component Declaration VHDL LIBRARY-USE Declaration
ALTIOBUF IP Core User Guide

ALTIOBUF Input, Output, and OE Paths

The three path types used with the I/O buffer in the delay chain architecture are input path, output path, and oe path.

Dynamic delay chains are integrated in the input path for input and bidirectional buffers. Dynamic delay chains are integrated in the output and oe paths for output and bidirectional buffers. This section describes the dynamic delay chain-related components only.

All paths share a similar configuration in which the delay cells are getting their delay control signal from the IO_CONFIG component. For the input path, the IO_CONFIG’s PADTOINPUTREGISTERDELAYSETTING output port drives the DELAY_CHAIN’s (input delay cell) DELAYCTRLIN input port. For the output and oe path, use the IO_CONFIG’s OUTPUTDELAYSETTING 1 and 2 output ports to drive the DELAYCTRLIN port of the first and second output delay cells, respectively.

The number of delay chains needed is NUMBER_OF_CHANNELS. Each instance of the I/O buffer includes a delay chain. Assume NUMBER_OF_CHANNELS is equal to ×. There must be × instances of input delay chain for × input buffer, and 2× instances of the first output delay chain and 2× instances of the second output delay chain output buffer because it uses the output and oe paths. The bidirectional buffer combines all instances of the delay chains mentioned above.

Figure 2. Sample ALTIOBUF (Input Buffer Mode) Architecture when NUMBER_OF_CHANNELS = 2This figure shows the internal architecture of the ALTIOBUF IP core (input buffer mode) when NUMBER_OF_CHANNELS is equal to 2 and the dynamic delay chain feature is enabled.
Level Two Title