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Ixiasoft
1.1. Software and Hardware Requirements
1.2. Download and Install the Tutorial Design Files
1.3. Open the Tutorial Project
1.4. Creating Qsys Systems
1.5. Assemble a Hierarchical System
1.6. Viewing the Memory Tester System in Qsys
1.7. Compiling and Downloading Software to a Development Board
1.8. Debugging Your Design
1.9. Verifying Hardware in System Console
1.10. Simulating Custom Components
1.11. View a Diagram of the Completed System
1.4.1.1. Create a New Qsys System and Set up the Clock Source
1.4.1.2. Add a Pipeline Bridge
1.4.1.3. Add a Custom Pattern Generator
1.4.1.4. Add a PRBS Pattern Generator
1.4.1.5. Add a Two-to-One Streaming Multiplexer
1.4.1.6. Verify the Memory Address Map
1.4.1.7. Connect the Reset Signals
1.4.1.8. Save the System
1.4.2.1. Create a New Qsys System and Set Up the Clock Soource
1.4.2.2. Add a Pipeline Bridge
1.4.2.3. Add a Custom Pattern Checker
1.4.2.4. Add the PRBS Pattern Checker
1.4.2.5. Add a One-to-Two Streaming Demultiplexer
1.4.2.6. Verify the Memory Address Map
1.4.2.7. Connect the Reset Signals
1.4.2.8. Save the System
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1.9.2. Add the JTAG-to-Avalon Master Bridge
The JTAG-to-Avalon master bridge acts as a bridge between the JTAG interface and the system's memory tester.
- In the IP Catalog select JTAG to Avalon Master Bridge, and then click Add.
- In the parameter editor, click Finish to accept the default parameters.
- Rename the instance to jtag_to_avalon_bridge.
- Connect the jtag_to_avalon_bridge master interface to the memory_tester_subsystem slave interface.
- Set the jtag_to_avalon_bridge clk domain to sdram_sysclk.
- Connect the jtag_avalon_bridge clk_reset interface to the ext_clk clk_reset interface.
- Connect the jtag_avalon_bridge clk_reset interface to either the sdram reset_request_n interface (for ALTMEMPHY-based designs), or sdram afi_reset interface (for UniPHY-based designs).
- Connect the jtag_avalon_bridge master_reset interface to the memory_tester_subsystem reset interface, and to either the sdram soft_reset_n interface (for ALTMEMPHY-based designs), or sdram soft_reset interface (for UniPHY-based designs).
- To disable the cpu_subsystem system, in the Use column, turn off Use, since you are replacing its function with the bridge and System Console.
- Save the jtag_to_avalon_bridge system.