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1.2.1. BMS Reference Design Software Requirements
1.2.2. BMS Reference Design Hardware Requirements
1.2.3. Downloading and Installing the BMS Reference Design
1.2.4. Setting Up the MAX 10 Development Board
1.2.5. Compiling the FPGA Hardware Design for the BMS Reference Design
1.2.6. Compiling the Nios Software for the BMS Reference Design
1.2.7. Programming the BMS Reference Design Hardware onto the Device
1.2.8. Downloading the BMS Reference Design Nios II Software to the Device
1.2.9. MATLAB Simulink Top-Level Design for the BMS Reference Design
1.2.10. Running the BMS Reference Design in a System-in-the-Loop Simulation
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1.3.4.1. BMS Reference Design Matrix Processor
The matrix processor is a generic matrix processor that Altera developed using the DSP Builder advanced blockset. It can perform sequences of different matrix operations.
You can select the maximum size of matrices to use to scale the usage of internal memory to fit the desired application. The matrix processor includes two data processing cores: Faddeev and matrix multiply cores. The Faddeev core can calculate the operation: D + C * A -1 * B. The matrix multiply core can calculate the (A * B) and (A * B + C) matrix expressions.
Figure 22. Matrix Processor Block Diagram
The matrix processor interface is the main interface between the matrix processor and the external environment. It programs the matrix processor for certain uCode, provides input matrix argumentss and reads-back results.