Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
2. About the DIB Intel® Stratix® 10 FPGA IP x
2.1. Release Information 2.2. Device Support for DIB Intel® Stratix® 10 FPGA IP 2.3. DIB Intel® Stratix® 10 FPGA IP Features 2.4. Latency
3. Functional Description x
3.1. Bypass Mode 3.2. Asynchronous Mode 3.3. Synchronous Mode
3.1. Bypass Mode x
3.1.1. AUX Channel Settings
4. Creating and Parameterizing the Intel FPGA IP x
4.1. IP Catalog and Parameter Editor 4.2. Creating a New Intel® Quartus® Prime Project 4.3. Parameterizing and Generating the IP 4.4. Compiling the DIB Intel® Stratix® 10 FPGA IP Design 4.5. Programming an FPGA Device
5. Designing with the DIB Intel® Stratix® 10 FPGA IP x
5.1. Reset Architecture 5.2. Clocking in Asynchronous and Synchronous Modes 5.3. Timing Closure 5.4. Setting Bypass, Asynchronous, and Synchronous Modes in One DIB Instance
5.2. Clocking in Asynchronous and Synchronous Modes x
5.2.1. Clocking Options 5.2.2. Clock Synchronization
5.3. Timing Closure x
5.3.1. Timing Transfer for Bypass Mode 5.3.2. Timing Transfer for TDM Modes
6. DIB Intel® Stratix® 10 FPGA IP Interface x
6.1. DIB Intel® Stratix® 10 FPGA IP Clocks 6.2. DIB Intel® Stratix® 10 FPGA IP User Interface Signals
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel

6.2. DIB Intel® Stratix® 10 FPGA IP User Interface Signals

The DIB Intel® Stratix® 10 FPGA IP uses the DIB control, data and DIB pad signals.
Table 10.  Control Signals
Signal Width Direction Description
iopll_locked 1 Input

When you set the DIB Channel Type parameter to Standard Channel, this signal connects to locked IOPLL when using a bank with TDM.

This signal is not applicable if you select AUX Channel.

dib_ready_n 1 Output This signal goes low when the DIB channel is ready.
Table 11.  DIB Pad Signals
Signal Width Direction Description
dib_pad_0 24 Input/Output

DIB pads for bank 0.

The direction of this signal depends on the mode of I/O bank 0.

dib_pad_1 24 Input/Output

DIB pads for bank 1.

The direction of this signal depends on the mode of I/O bank 1.

dib_pad_2 24 Input/Output

DIB pads for bank 2.

The direction of this signal depends on the mode of I/O bank 2.

dib_pad_3 24 Input/Output

DIB pads for bank 3.

The direction of this signal depends on the mode of I/O bank 3.

Table 12.  DIB RX Data Signals
Signal Width Direction Description
core_rx_data_0 82 Output

Core data RX interface for bank 0.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

core_rx_data_1 82 Output

Core data RX interface for bank 1.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

core_rx_data_2 82 Output

Core data RX interface for bank 2.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

core_rx_data_3 82 Output

Core data RX interface for bank 3.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

Table 13.  DIB TX Data Signals
Signal Width Direction Description
core_rx_data_0 82 Input

Core data TX interface for bank 0.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

core_rx_data_1 82 Input

Core data TX interface for bank 1.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

core_rx_data_2 82 Input

Core data TX interface for bank 2.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

core_rx_data_3 82 Input

Core data TX interface for bank 3.

  • Bypass: Connect to [21:0]
  • TDM 1:1: Connect to [21:2], [1:0] reserved
  • TDM 2:1: Connect to [41:2], [1:0] reserved
  • TDM 4:1: Connect to [81:2], [1:0] reserved

The direction of this signal depends on the mode of I/O bank 0.

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