Direct Interface Bus (DIB) Intel® Stratix® 10 FPGA IP User Guide

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ID 683142
Date 3/18/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide 2. About the DIB Intel® Stratix® 10 FPGA IP 3. Functional Description 4. Creating and Parameterizing the Intel FPGA IP 5. Designing with the DIB Intel® Stratix® 10 FPGA IP 6. DIB Intel® Stratix® 10 FPGA IP Interface 7. DIB Intel® Stratix® 10 FPGA IP Parameters 8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide A. Die-to-Die Mapping B. Example Pin Locations for One DIB Channel
2. About the DIB Intel® Stratix® 10 FPGA IP x
2.1. Release Information 2.2. Device Support for DIB Intel® Stratix® 10 FPGA IP 2.3. DIB Intel® Stratix® 10 FPGA IP Features 2.4. Latency
3. Functional Description x
3.1. Bypass Mode 3.2. Asynchronous Mode 3.3. Synchronous Mode
3.1. Bypass Mode x
3.1.1. AUX Channel Settings
4. Creating and Parameterizing the Intel FPGA IP x
4.1. IP Catalog and Parameter Editor 4.2. Creating a New Intel® Quartus® Prime Project 4.3. Parameterizing and Generating the IP 4.4. Compiling the DIB Intel® Stratix® 10 FPGA IP Design 4.5. Programming an FPGA Device
5. Designing with the DIB Intel® Stratix® 10 FPGA IP x
5.1. Reset Architecture 5.2. Clocking in Asynchronous and Synchronous Modes 5.3. Timing Closure 5.4. Setting Bypass, Asynchronous, and Synchronous Modes in One DIB Instance
5.2. Clocking in Asynchronous and Synchronous Modes x
5.2.1. Clocking Options 5.2.2. Clock Synchronization
5.3. Timing Closure x
5.3.1. Timing Transfer for Bypass Mode 5.3.2. Timing Transfer for TDM Modes
6. DIB Intel® Stratix® 10 FPGA IP Interface x
Top-Level Signals for Each DIB Channel 6.1. DIB Intel® Stratix® 10 FPGA IP Clocks 6.2. DIB Intel® Stratix® 10 FPGA IP User Interface Signals
1. About the DIB Intel® Stratix® 10 FPGA IP User Guide
2. About the DIB Intel® Stratix® 10 FPGA IP
3. Functional Description
4. Creating and Parameterizing the Intel FPGA IP
5. Designing with the DIB Intel® Stratix® 10 FPGA IP
6. DIB Intel® Stratix® 10 FPGA IP Interface
7. DIB Intel® Stratix® 10 FPGA IP Parameters
8. Document Revision History for the DIB Intel® Stratix® 10 FPGA IP User Guide
A. Die-to-Die Mapping
B. Example Pin Locations for One DIB Channel

6. DIB Intel® Stratix® 10 FPGA IP Interface

All the interfaces for each DIB channel are always present. Unused signals are not connected.
The DIB Intel® Stratix® 10 FPGA IP has three main interface signals:
  • Control
  • Data
  • DIB Pad

The direction of the DIB pad signals are dynamically generated based on your settings in the parameter editor.

All standard and AUX channels have the same top-level signals.

Top-Level Signals for Each DIB Channel

module my_dib (
      output wire [81:0] core_rx_data_0,
      output wire [81:0] core_rx_data_1,
      output wire [81:0] core_rx_data_2,
      output wire [81:0] core_rx_data_3,
      input  wire [81:0] core_tx_data_0,
      input  wire [81:0] core_tx_data_1,
      input  wire [81:0] core_tx_data_2,
      input  wire [81:0] core_tx_data_3,
      input  wire        dib_clk,
      output wire        dib_ready_n,
      input  wire        iopll_locked,
      input  wire [23:0] dib_pad_0,
      output wire [23:0] dib_pad_1,
      input  wire [23:0] dib_pad_2,
      output wire [23:0] dib_pad_3,
      output wire        rem_clk,
      input  wire        sys_clk
   );
endmodule

Section Content
DIB Intel Stratix 10 FPGA IP Clocks
DIB Intel Stratix 10 FPGA IP User Interface Signals

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