Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813899
Date 4/01/2024
Public

1.4. Compiling the Design Example

To compile the hardware design example, follow these steps:

  1. Ensure hardware design example generation is complete.
  2. In the Quartus® Prime Pro Edition software, open the Quartus® Prime project <design_example_dir>/hardware_test_design/intel_eth_tse_hw.qpf .
  3. On the Processing menu, click Start Compilation.