Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813899
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver 3. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Simulating the Triple-Speed Ethernet Intel® FPGA IP Design Example Testbench 1.4. Compiling the Design Example
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Interface Signals
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench
1. Quick Start Guide
2. 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS with GTS Transceiver
3. Document Revision History for the Triple-Speed Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

1.1. Directory Structure

The Triple-Speed Ethernet Intel® FPGA IP design example file directories contain the following generated files for the 10/100/1000 Ethernet MAC Design Example with 1000BASE-X/SGMII 2XTBI PCS:
  • The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design.
  • The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
  • The compilation-only design example is located in <design_example_dir>/compilation_test_design.
  • The compilation test and hardware test designs use files in <design_example_dir>/ex_tse/common.
Figure 2. Directory Structure for the Design Example
Table 1.  Testbench File Description
Directory/File Description
Testbench and Simulation Files
<design_example_dir>/example_testbench/basic_avl_tb_top_2xtbi_pma_ag.sv Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/example_testbench/ basic_avl_tb_top_2xtbi_pma_ag_msim.sv Top-level testbench file for QuestaSim* simulation. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
<design_example_dir>/example_testbench/ basic_avl_tb_top_2xtbi_pma_ag_nc.sv Top-level testbench file for Xcelium* simulation. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets.
Testbench Scripts
<design_example_dir>/example_testbench/ run_vsim_2xtbi_pma.do The QuestaSim* script to run the testbench.
<design_example_dir>/example_testbench/run_vcs_2xtbi_pma.sh The Synopsys* VCS script to run the testbench.
<design_example_dir>/example_testbench/run_vcsmx_2xtbi_pma.sh The Synopsys* VCS MX script to run the testbench
<design_example_dir>/example_testbench/run_xcelium_2xtbi_pma.sh The Xcelium* script to run the testbench.
Table 2.  Hardware Design Example File Description
Directory/File Description

<design_example_dir>/hardware_test_design/ intel_eth_tse_hw.qpf

Quartus® Prime project file.

<design_example_dir>/hardware_test_design/ intel_eth_tse_hw.qsf

Quartus® Prime project settings file.

<design_example_dir>/hardware_test_design/intel_eth_tse_hw.sdc

Synopsys* Design Constraints files. You can copy and modify these files for your own design.

<design_example_dir>/hardware_test_design/ intel_eth_tse_hw.v

Top-level Verilog HDL design example file.

<design_example_dir>/hardware_test_design/common/

Hardware design example support files.
Level Two Title