Intel Cyclone 10 LP Device Design Guidelines

Download PDF
ID 683861
Date 3/28/2019
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Design Guidelines
Intel® Cyclone® 10 LP Device Design Guidelines x
Design Flow System Specification Device Selection Early System and Board Planning Pin Connection Considerations for Board Design I/O and Clock Planning Design Entry Design Implementation, Analysis, Optimization, and Verification Document Revision History for Intel® Cyclone® 10 LP Device Design Guidelines
System Specification x
Design Specifications IP Selection Platform Designer
Device Selection x
Device Variant PLLs and Clock Routing Logic, Memory, and Multiplier Density I/O Pin Count, LVDS Channels, and Package Offering Speed Grade Vertical Device Migration
Early System and Board Planning x
Early Power Estimation Planning for Device Configuration Planning for On-chip Debugging
Planning for Device Configuration x
Configuration Scheme Selection Configuration Features Intel® Quartus® Prime Configuration Settings
Configuration Scheme Selection x
Serial Configuration Devices Download Cables
Intel® Quartus® Prime Configuration Settings x
Optional Configuration Pins
Planning for On-chip Debugging x
On-chip Debugging Tools Planning Guidelines for Debugging Tools
Pin Connection Considerations for Board Design x
Device Power-Up Power Pin Connections and Power Supplies Configuration Pin Connections Board-related Intel® Quartus® Prime Settings Signal Integrity Considerations Board-level Simulation and Advanced I/O Timing Analysis
Power Pin Connections and Power Supplies x
Decoupling Capacitors PLL Board Design Guidelines
Configuration Pin Connections x
Clock Trace Signal Integrity JTAG Pins MSEL Configuration Mode Pins Other Configuration Pins
JTAG Pins x
JTAG Pin Connections Download Cable Operating Voltage JTAG Signal Buffering
Board-related Intel® Quartus® Prime Settings x
Device-wide Output Enable Pin Unused Pins
Signal Integrity Considerations x
Voltage Reference Pins Simultaneous Switching Noise I/O Termination
I/O and Clock Planning x
Making FPGA Pin Assignments Early Pin Planning and I/O Assignment Analysis I/O Features and Pin Connections Clock and PLL Selection PLL Feature Guidelines Clock Control Features I/O Simultaneous Switching Noise
I/O Features and Pin Connections x
I/O Signaling Type Selectable Standards and Flexible I/O Banks Dual-Purpose and Special Pin Connections Intel® Cyclone® 10 LP I/O Features
PLL Feature Guidelines x
Clock Feedback Mode Clock Outputs
Design Entry x
Design Recommendations Using IP Cores Recommended HDL Coding Styles Register Power-up Levels and Control Signals
Design Implementation, Analysis, Optimization, and Verification x
Selecting a Synthesis Tool Device Resource Utilization Reports Intel® Quartus® Prime Messages Timing Constraints and Analysis Area and Timing Optimization Preserving Performance and Reducing Compilation Time Simulation Power Analysis Power Optimization
Timing Constraints and Analysis x
Recommended Timing Optimization and Analysis Assignments
Power Optimization x
Device and Design Power Optimization Techniques Intel® Quartus® Prime Power Optimization Techniques
Device and Design Power Optimization Techniques x
Clock Power Management Memory Power Reduction I/O Power Guidelines
Intel® Cyclone® 10 LP Device Design Guidelines

Device Power-Up

Table 21.  Device Power-Up Checklist
Number Done? Checklist Item
1   Design board for power-up: All Intel® Cyclone® 10 LP GPIO pins are tri-stated until the device is configured and the configuration pins drive out.
2   Design voltage power supply ramps to be monotonic.
3   Set POR time to ensure power supplies are stable.

Intel® Cyclone® 10 LP device I/O pins are hot-socketing compliant without external components. You can insert or remove a Intel® Cyclone® 10 LP device from a powered-up system board without damaging or interfering with normal system and board operation.

You can drive signals into the I/O pins before or during power up or power down without damaging the device. Intel® Cyclone® 10 LP devices support power up or power down of the VCCINT, VCCA, and VCCIO pins in any sequence to simplify the system level design. The individual power supply ramp-up and ramp-down rates can range from 50 µs to 50 ms. The power ramp must be monotonic.

In a hot-socketing situation, the Intel® Cyclone® 10 LP device’s output buffers are turned off during system power up or power down. Also, the Intel® Cyclone® 10 LP device does not drive out until the device is configured and working within the recommended operating conditions.

Hot-socketing circuitry is not available on CONF_DONE, nCEO, and nSTATUS configuration pins because they are required during configuration. Therefore, it is expected behavior for these pins to drive out during power-up and power-down sequences.

The POR circuit keeps the entire system in reset until the power supply voltage levels have stabilized after power up. After power up, the device does not release nSTATUS until VCCINT, VCCA, and VCCIO for the I/O banks that contain configuration pins are above the POR trip point of the device. After power down, brown-out occurs if the VCCINT or VCCA voltage sags below the POR trip point. In Intel® Cyclone® 10 LP devices, you can select a fast or standard POR time, depending on the MSEL pin settings. The fast POR time is 3 ms < TPOR < 9 ms for a fast configuration time. The standard POR time is 50 ms < TPOR < 200 ms, which has a lower power-ramp rate.

When power is applied to a Intel® Cyclone® 10 LP device, a POR event occurs if the power supply reaches the recommended operating range within a certain period of time (specified as a maximum power supply ramp time; tRAMP). The maximum power supply ramp time for Intel® Cyclone® 10 LP devices is 50 ms for standard POR or 3 ms for fast POR, while the minimum power supply ramp time is 50 µs.

Level Two Title