OCT Intel® FPGA IP User Guide

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ID 683708
Date 7/03/2019
Public
Document Table of Contents
Document Table of Contents x
OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP User Guide x
OCT Intel® FPGA IP Features OCT Intel® FPGA IP Overview OCT Intel® FPGA IP Functional Description OCT Intel® FPGA IP Design Example OCT Intel® FPGA IP References OCT Intel® FPGA IP User Guide Archives Document Revision History for OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP Overview x
RZQ Pin OCT Block OCT Logic
OCT Intel® FPGA IP Functional Description x
Power-Up Mode Interfaces User Mode OCT
User Mode OCT x
Core FSM
OCT Intel® FPGA IP Design Example x
Generating the Intel® Quartus® Prime Design Example
OCT Intel® FPGA IP References x
OCT Intel® FPGA IP Parameter Settings OCT Intel® FPGA IP Signals QSF Assignments IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTOCT IP to the OCT Intel® FPGA IP
OCT Intel® FPGA IP User Guide

OCT Intel® FPGA IP Parameter Settings

Table 3.   OCT IP Parameters
Name Value Description
Number of OCT blocks 1 to 12 Specifies the number of OCT blocks to be generated. The default value is 1.
Use backwards-compatible port names
  • On
  • Off
 Check this to use legacy top-level names compatible with the ALTOCT IP. This parameter is disabled by default.
OCT mode
  • Power-up
  • User
 Specifies whether OCT is user-controllable or not. The default value is Power-up.
OCT block x calibration mode
  • Single
  • Double
  • POD
 Specifies the calibration mode for the OCT. X corresponds to the number of the OCT block. The default value is Single.
Level Two Title