OCT Intel® FPGA IP User Guide

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ID 683708
Date 7/03/2019
Public
Document Table of Contents
Document Table of Contents x
OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP User Guide x
OCT Intel® FPGA IP Features OCT Intel® FPGA IP Overview OCT Intel® FPGA IP Functional Description OCT Intel® FPGA IP Design Example OCT Intel® FPGA IP References OCT Intel® FPGA IP User Guide Archives Document Revision History for OCT Intel® FPGA IP User Guide
OCT Intel® FPGA IP Overview x
RZQ Pin OCT Block OCT Logic
OCT Intel® FPGA IP Functional Description x
Power-Up Mode Interfaces User Mode OCT
User Mode OCT x
Core FSM
OCT Intel® FPGA IP Design Example x
Generating the Intel® Quartus® Prime Design Example
OCT Intel® FPGA IP References x
OCT Intel® FPGA IP Parameter Settings OCT Intel® FPGA IP Signals QSF Assignments IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices
IP Migration Flow for Arria® V, Cyclone® V, and Stratix® V Devices x
Migrating Your ALTOCT IP to the OCT Intel® FPGA IP
OCT Intel® FPGA IP User Guide

OCT Logic

The OCT block sends the calibration code words serially to the OCT logic through the ser_data ports.

The enser signal, when triggered, specifies from which OCT block to read the calibration code words. The calibration code words are then buffered into the serial-to-parallel shift logic. After that, the s2pload signal automatically asserts to send the calibration code words in parallel to the I/O buffers.

The calibration code words activate or deactivate the transistors in the I/O block, which will emulate series or parallel resistance to match the impedance.

Figure 2. Internals of OCT Logic


Level Two Title