Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/20/2023
Public

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5.3.2.4.1. Avalon® Streaming Ready to Credit Adapter Interface Parameters

You can specify the following parameters for the Avalon® Streaming Ready to Credit Adapter by double-clicking Avalon Streaming Ready to Credit Intel FPGA IP in the Platform Designer IP Catalog:

Table 75.   Avalon® Streaming Ready to Credit Adapter Interface Parameters
Parameter Name Description Legal Values
Maximum Credit Allowed (Sink Interface) Specifies the maximum number of credits allowed by the sink interface. Legal values are from 1 to 256. 1,2,4,8,16,32,64,128,256
Number of symbols Specifies the maximum number of symbols that can transfer. 1-8192
Symbol width Specifies the number of data bits per symbol. 1-8192
Width of Channel Port

The width of the channel signal on the data interfaces. This parameter is disabled when Use Channel is disabled.

1-128
Width of Error Port

The width of the error signal on the output interfaces. A value of 0 indicates that the error signal is not in use. This parameter is disabled when Use Error is disabled.

1-1024
Width of Empty Port

The width of the empty signal on the output interfaces. A value of 0 indicates that the empty signal is not in use. This parameter is disabled when Use Empty is disabled.

1-1024
Ready Latency Specifies the ready latency to expect from the sink connected to the module's source interface. 0-32
synchronous reset Specifies that the adapter should have a synchronous reset. On|Off
Use Packets

Indicates whether data packet transfers are supported. Packet support includes the startofpacket, endofpacket, and empty signals.

On|Off
Use Empty

Enables or disables the empty signal.

On|Off
Use Channel

Enables or disables the channel signal.

On|Off
Use Error

Enables or disables the error signal.

On|Off