Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 12/20/2023
Public

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Document Table of Contents

5.16. Platform Designer Interconnect Revision History

The following revision history applies to this chapter:

Document Version Intel® Quartus® Prime Version Changes
2023.10.02 23.3
  • Removed misplaced Reset Synchronous Edges description from Clock Interfaces topic.
  • Removed obsolete upper limit from IRQ Fan-Out topic.
2023.04.03 23.1
  • The product family name is updated to "Intel Agilex 7" to reflect the different family members.
2022.06.20 22.2
  • Added new IRQ Fanout topic.
  • Updated IRQ Mapper topic to describe Remove Clock and Reset Ports parameters.
  • Updated legal IRQ width from 32 to 2048 in the following topics:
    • Interrupt Interfaces
    • Individual Requests IRQ Scheme
    • Avalon® Interrupt Sender Signal Roles
    • Avalon® Interrupt Receiver Signal Roles
2022.04.02 22.1
  • Updated entire chapter for new AXI "manager" and AXI "subordinate" replacement terms. Refer to the AMBA® AXI and ACE Protocol Specification.
  • Updated parameter values for all Avalon® Streaming Credit IPs.
  • Revised wording in Terms and Concepts topic for greater clarity.
  • Revised AMBA* 4 AXI-Lite Signals topic for optional signals information.
  • Added new AMBA* 4 AXI-Lite Optional Port Support and Interconnect topic describing optional port support details.
2021.03.29 21.1
  • Converted to "host" and "agent" inclusive terminology for Avalon® memory mapped interface descriptions and related GUI elements throughout.
2020.12.14 20.4
  • Revised "Interconnect Pipelining" for clarity and latest GUI.
  • Revised "Fixed Priority Arbitration" for latest GUI.
  • Revised "Add Pipeline Stages in the Interconnect Schematic" for Add All Pipelines and Remove All Pipelines controls.
  • Revised statement in "Ordering Model" topic to clarify applies to all versions.
  • Revised "Pipeline Placement in Arbitration Logic" diagram color coding.
2020.06.26 20.1

Removed incorrect statement about compile time option to enforce strict ordering from the "AXI and Avalon Ordering" topic.

2020.05.08 20.1

Added some clarification for the timing behavior of the signal writeresponsevalid to the Avalon® Memory-Mapped Interface Signal Roles section.

Updated the bus widths for the data and empty signals in the Avalon® Streaming Interface Signal Roles section.

2020.05.01 20.1
  • Updated " Avalon® Streaming Credit Interface Signal Roles" to indicate that return_credit is required.
  • Added " Avalon® Streaming Credit Interfaces" section.
  • Added " Avalon® Streaming Credit Interface Signal Roles" topic.
  • Added " Avalon® Streaming Credit User Signals" topic.
2019.11.11 19.1.0
  • Added note to "Burst Adaptation: AXI to Avalon® " about AXI3 and AXI4 4KB boundary restriction for burst transactions.
  • Added "Adjacent Bytelanes with Partial Width Transactions" topic.
2019.06.19 19.1.0
  • Corrected statement about preventing reordering in "Ordering Model."
2019.04.01 19.1.0
  • Described new default use of synchronous reset option for Intel® Stratix® 10 designs in "Reset Interfaces."
2018.12.10 18.1.0
  • Replaced references to System Contents tab with new System View tab.
2018.09.24 18.1.0
  • Updated location of Limit interconnect pipeline stages to option in Platform Designer GUI
  • In Avalon Memory-Mapped Interface Signal Roles, added consecutive byte-enable support.
  • Specified minimum duration of reset that the Platform Design Interconnect requires to work correctly.
2018.06.15 18.0.0 Clarified behavior of Error Correction Coding (ECC) in Interconnect.
2018.05.07 18.0.0
  • Added support for waitrequestAllowance adapter.
  • Added support for ACE-Lite connections.
2017.11.06 17.1.0
  • Changed instances of Qsys Pro to Platform Designer
  • Updated information about the Reset Sequencer.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
  • Implemented Qsys rebranding.
2015.11.02 15.1.0 Changed instances of Quartus II to Quartus Prime.
2015.05.04 15.0.0
  • Fixed Priority Arbitration.
  • Added topic: Read and Write Responses.
  • Added topic: Error Correction Coding (ECC) in Qsys Interconnect.
  • Added: response [1:0], Avalon Memory-Mapped Interface Signal Roles.
  • Added writeresponsevalid, Avalon Memory-Mapped Interface Signal Roles.
December 2014 14.1.0
  • Read error responses, Avalon Memory-Mapped Interface Signal, response.
  • Burst Adapter Implementation Options: Generic converter (slower, lower area), Per-burst-type converter (faster, higher area).
August 2014 14.0a10.0
  • Updated Qsys Packet Format for Memory-Mapped Host and Agent Interfaces table, Protection.
  • Streaming Interface renamed to Avalon Streaming Interfaces.
  • Added Response Merging under Memory-Mapped Interfaces.
June 2014 14.0.0
  • AXI4-Lite support.
  • AXI4-Stream support.
  • Avalon streaming adapter parameters.
  • IRQ Bridge.
  • Handling Read Side Effects note added.
November 2013 13.1.0
  • HSSI clock support.
  • Reset Sequencer.
  • Interconnect pipelining.
May 2013 13.0.0
  • AMBA APB support.
  • Auto-inserted Avalon streaming adapters feature.
  • Moved Address Span Extender to the Qsys System Design Components chapter.
November 2012 12.1.0
  • AMBA AXI4 support.
June 2012 12.0.0
  • AMBA AXI3 support.
  • Avalon streaming adapters.
  • Address Span Extender.
November 2011 11.0.1 Template update.
May 2011 11.0.0 Removed beta status.
December 2010 10.1.0 Initial release.