Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes

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Date 7/08/2017
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1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes
1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes x
1.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.1 1.2. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.0 1.3. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.1 1.4. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0 Arria 10 Edition
1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes

1.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.1

Table 1.  Version 15.1 November 2015Arria 10 support for this IP core is available in the Altera MegaCore IP Library. Stratix V support is available only through the Self-Service Licensing center.
Description Impact Notes
In Arria 10 variations. added new parameters Enable Altera Debug Master Endpoint and Enable ODI acceleration logic. Upgrading the IP core to incorporate these features is optional. This change does not affect the top-level signals of the IP core. These parameters expose control of transceiver configuration features.
Made comprehensive changes to 1588 PTP interfaces. Upgrading the IP core to incorporate this feature is optional. In variations that include the 1588 PTP support feature, the interface changes modify and add top-level output signals to the IP core. Therefore, to utilize the 1588 PTP support feature after you upgrade, you must reconnect the IP core in your design. Refer to LL 40-100GbE IP Core Signal Changes v15.1 table.
Added new 1588 PTP parameters Enable 96b Time of Day Format, Enable 64b Time of Day Format, and Timestamp fingerprint width. Upgrading the IP core to incorporate this feature is optional. These parameters are available only if you turn on the Enable 1588 PTP parameter.  
Removed TX_PTP_STATUS register. Upgrading the IP core to incorporate this feature is optional. If you upgrade your IP core to the v15.1 version, you must be aware of this change in variations that include the 1588 PTP support feature.  
Added new 1588 PTP registers TX_PTP_ASYM_DELAY, TX_PTP_PMA_LATENCY, and RX_PTP_PMA_LATENCY. Upgrading the IP core to incorporate this feature is optional. If you upgrade your IP core to the v15.1 version, you must be aware of these changes in variations that include the 1588 PTP support feature.
Added dedicated Example Design tab in parameter editor for Arria 10 variations. Upgrading the IP core to incorporate this feature is optional. If you upgrade your IP core, you should use the Example Design tab to generate a testbench and design example that work correctly with the upgraded IP core.  
Added hardware test you can run on the hardware design example. Upgrading the IP core and regenerating the example design to incorporate this feature is optional. If you upgrade the IP core but do not regenerate the example design, this feature is not available.  
Minor changes to LL 40GBASE-KR4 feature register default values. If you upgrade your IP core to the v15.1 version, you must be aware of these changes in LL 40GBASE-KR4 variations.
Table 2.  LL 40-100GbE IP Core Signal Changes v15.1All signal changes are associated with the PTP module. Signals added or modified in version 15.1 are due to a comprehensive change in the 1588 PTP interface. All correspondences between old and new signal names are approximate: many of the new signals indicate a combination of old signal values or incorporate information previously available in the TX_PTP_STATUS register. Other signals are added for the new 64-bit timestamp option.

Notes specify the expected usage of the new signal. In most cases the output signals are in fact available in the other processing modes and your design can use them in other processing modes. For full information about the sets of mutually exclusive input signals, refer to the LL 40-100GbE IP core user guide.

Old Signal Name New Signal Name Notes
tod_rxmac_in[95:0] rx_time_of_day_96b_data[95:0] RX PTP interface to TOD module: Two distinct signals to support the Enable 96b Time of Day Format and Enable 64b Time of Day Format parameters.
rx_time_of_day_64b_data[63:0]
tod_txmac_in[95:0] tx_time_of_day_96b_data[95:0] TX PTP interface to TOD module: Two distinct signals to support the Enable 96b Time of Day Format and Enable 64b Time of Day Format parameters.
tx_time_of_day_64b_data[63:0]
rx_tod[95:0] rx_ingress_timestamp_96b_data[95:0] RX PTP interface to TOD module: Two distinct signals to support the Enable 96b Time of Day Format and Enable 64b Time of Day Format parameters.
rx_ingress_timestamp_64b_data[63:0]
— rx_ingress_timestamp_96b_valid RX PTP interface: Valid signal for rx_ingress_timestamp_96b_data.
— rx_ingress_timestamp_64b_valid RX PTP interface: Valid signal for rx_ingress_timestamp_64b_data.
tx_in_ptp tx_egress_timestamp_request_valid Incorporates functionality of old tx_in_ptp signal (tells the IP core the current incoming packet on the TX client interface is a PTP packet) and also tells the IP core to process this packet in two-step processing mode.
tx_etstamp_ins_ctrl_timestamp_insert Incorporates functionality of old tx_in_ptp signal (tells the IP core the current incoming packet on the TX client interface is a PTP packet) and also tells the IP core to process this packet in one-step processing insertion mode.
tx_etstamp_ins_ctrl_residence_time_update Incorporates functionality of old tx_in_ptp signal (tells the IP core the current incoming packet on the TX client interface is a PTP packet) and also tells the IP core to process this packet in tone-step processing correction mode.
tod_tx_clk_st2[95:0] tx_egress_timestamp_96b_data[95:0] TX PTP two-step processing: Two distinct signals to support the Enable 96b Time of Day Format and Enable 64b Time of Day Format parameters.
tx_egress_timestamp_64b_data[63:0]
ptp_pkt_out tx_egress_timestamp_96b_valid TX PTP two-step processing: Two distinct signals to support the Enable 96b Time of Day Format and Enable 64b Time of Day Format parameters.
tx_egress_timestamp_64b_valid
— tx_egress_timestamp_request_fingerprint TX PTP fingerprint: Fingerprint in.
— tx_egress_timestamp_96b_fingerprint TX PTP fingerprint: Fingerprint out (96-bit timestamp interface).
— tx_egress_timestamp_64b_fingerprint TX PTP fingerprint: Fingerprint out (64-bit timestamp interface).
tx_in_ptp_overwrite[1:0] —  
— tx_etstamp_ins_ctrl_timestamp_format TX PTP one-step processing insertion mode: timestamp format (96-bit or 64-bit).
— tx_etstamp_ins_ctrl_residence_time_calc_format TX PTP one-step processing correction mode: latency format (96-bit or 64-bit).
tx_in_ptp_offset[15:0] tx_etstamp_ins_ctrl_offset_timestamp[15:0] TX PTP one-step processing insertion mode: timestamp offset.
tx_etstamp_ins_ctrl_offset_correction_field[15:0] TX PTP one-step processing correction mode: correction field offset. Also the location for two bytes of inserted 96-bit timestamp (in insertion mode).
— tx_etstamp_ins_ctrl_ingress_timestamp_96b[95:0] TX PTP one-step processing: 96-bit entry timestamp.
— tx_etstamp_ins_ctrl_ingress_timestamp_64b[63:0] TX PTP one-step processing: 64-bit entry timestamp.
tx_in_zero_tcp tx_etstamp_ins_ctrl_checksum_zero TX PTP one-step processing: Set checksum to the value of zero.
tx_etstamp_ins_ctrl_checksum_correct TX PTP one-step processing: Update the checksum following the timestamp update.
tx_in_tcp_offset[15:0] tx_etstamp_ins_ctrl_offset_checksum_field[15:0] TX PTP one-step processing, offset to zero the checksum (required if you assert tx_etstamp_ins_ctrl_checksum_zero).
tx_etstamp_ins_ctrl_offset_checksum_correction[15:0] TX PTP one-step processing, offset to update (correct) the checksum (required if you assert tx_etstamp_ins_ctrl_checksum_correct).
— tx_egress_asymmetry_update Tells the IP core to use the value in the new TX_PTP_ASYM_DELAY register.
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