Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes

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Date 7/08/2017
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1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes
1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes x
1.1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.1 1.2. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v15.0 1.3. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.1 1.4. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.0 Arria 10 Edition
1. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core Release Notes

1.3. Low Latency 40- and 100-Gbps Ethernet MAC and PHY IP Core v14.1

Table 5.  Version 14.1 December 2014Arria 10 support for this IP core is available in the Altera MegaCore IP Library. Stratix V support is available only through the Self-Service Licensing center.
Description Impact Notes
The Quartus II software v14.1 requires that you specify a device if your IP core targets the Arria 10 device family. If you do not specify your target Arria 10 device, the IP Upgrade tool insists that your IP core requires upgrade, but does not clarify the reason. You must ensure that you specify a device for your v14.0 Arria 10 Edition IP core variation and regenerate it in the Quartus II software v14.1.

Added optional 40GBASE-KR4 support in LL 40GbE IP core variations. Turning on the Enable KR4 parameter makes many additional 40GBASE-KR4 specific parameters available. 40GBASE-KR4 variations have many additional registers but no additional signals.

Upgrading the IP core to incorporate this feature is optional. This feature does not affect the top-level signals of the IP core.
All statistics increment vectors are now available and functional whether or not you include the relevant statistics counters in your IP core variations. Previously, the statistics increment vectors were functional only in IP core variations that included the relevant statistics module. Upgrading the IP core to incorporate this feature is optional. This feature does not affect the top-level signals of the IP core.
Added option to move the TX MAC PLL outside the IP core. Turning on the Use external TX MAC PLL parameter adds an input clock that drives the clk_txmac internal clock. This option adds no additional registers or register fields. Upgrading the IP core to incorporate this feature is optional. This feature does not affect the top-level signals of the IP core unless you turn on the Use external TX MAC PLL parameter. Refer to LL 40-100GbE IP Core Signal Changes table.
Added two new 64-bit statistics counters RXOctets_OK at offset 0x960 and TXOctets_OK at offset 0x860 to count the payload bytes (octets) in received and transmitted frames with no FCS errors, undersized, oversized, or payload length errors. The two registers each have two associated new signals. Upgrading the IP core to incorporate this feature is optional. If you upgrade the IP core to the v14.1 version, this feature adds top-level signals and therefore requires that you reconnect the IP core in your design. Refer to LL 40-100GbE IP Core Signal Changes table.
Added new CFG_PLEN_CHECK register at offset 0x50A to support bit[4] of the new six-bit RX error signal. If you upgrade your IP core to the v14.1 version and wish to use the new length checking status flag, you must ensure that user logic turns on the enable bit in this new register. In addition, the register supports a new RX error status flag signal that requires that you reconnect the IP core in your design.
Changed handling of received malformed packet. If the IP core detects an incoming unexpected control character, it generates an EOP for the packet. Previously the IP core did not terminate (generate an EOP for) an incoming packet if it received an unexpected control character. In addition the IP core signals an error on the new six-bit RX error status signal when appropriate. If you upgrade your IP core to the v14.1 version, you must be aware of this behavior change.
Newly generated IP cores do not have top-level signals that interface to modules that the IP core does not include. This change applies to the TX MAC input clock, link fault signals, pause signals, and PTP signals. Because of the backward compatibility feature described in the Notes column, if you upgrade your IP core to the v14.1 version, this feature has no effect on the top-level signals and does not require any additional actions. Note that this feature applies only to IP core variations that do not instantiate the relevant module or modules. For backward compatibility, if you upgrade an IP core variation, link fault signals, pause top-level signals, and PTP signals in the earlier release of the IP core variation remain available in the 14.1 version after upgrade.
Updated PTP module behavior and modified parameter name. If you turn on Enable 1588 PTP, the PTP module has the following new features and requirements:
  • You must instantiate a time-of-day (TOD) module and connect it to the IP core.
  • Added new PTP signals to receive the timestamps the TOD module generates in the two clock domains. Refer to LL 40-100GbE IP Core Signal Changes table.
  • Removed TX PTP module TOD calculation registers at offsets 0xB06 through 0xB08. The TOD module now provides the functionality the registers supported in previous versions of the IP core.
  • Added support for resetting the TCP checksum to zero of the application does not recalculate it. Added two new signals with which the application communicates such a request to the IP core. Refer to LL 40-100GbE IP Core Signal Changes table.
Upgrading the IP core to incorporate this feature is optional. If you upgrade the IP core to the v14.1 version, and the PTP module is included in your original IP core variation, this feature adds top-level signals and therefore requires that you reconnect the IP core in your design.
Improved RX skew tolerance to 1900 bits for LL 40GbE IP core variations and to 1000 bits for LL 100GbE IP core variations. Altera LL 40-100GbE IP cores exceed the IEEE 802.3-2012 Ethernet Standard Clause 82.2.12 requirements of 1856 bits skew tolerance for 40GbE IP cores and 928 bits skew tolerance for 100GbE IP cores.
Table 6.  LL 40-100GbE IP Core Signal ChangesSignals added or modified in version 14.1.
Old Signal Name New Signal Name Notes
— clk_txmac_in Input clock to drive the clk_txmac internal clock. This signal is available if you turn on Use external TX MAC PLL in the LL 40-100GbE parameter editor.
l<n>_rx_error (1 bit) l<n>_rx_error[5:0] (Avalon-ST client interface) New six-bit RX error status signal.
— rx_error[5:0] (custom client interface)
— unidirectional_en Signals that provide status from the LINK_FAULT_CONFIG register.
— link_fault_gen_en
— tx_inc_octetsOK[15:0] Signals that provide per-frame information associated with the new RxOctets_OK and TXOctets_OK registers. These signals are present and functional whether or not you turn on Enable TX statistics or Enable RX statistics in the parameter editor.
— tx_inc_octetsOK_valid
— rx_inc_octetsOK[15:0]
— rx_inc_octetsOK_valid
— tx_in_zero_tcp Signals for application to direct the IP core to reset the TCP checksum field.
— tx_in_tcp_offset[15:0]
— tod_txmac_in[95:0] Signals to receive TOD values from new external TOD module.
— tod_rxmac_in[95:0]
Link fault signals are present in new IP core variations you generate in the Quartus II v14.1 IP Catalog only if you turn on Enable link fault generation in the parameter editor. For backward compatibility, the signals remain if you upgrade from a pre-14.1 IP core variation that has those signals.
Pause signals are present in new IP core variations that you generate in the Quartus II v14.1 IP Catalog only if you set Flow control mode to standard flow control or priority-based flow control in the parameter editor. For backward compatibility, the signals remain if you upgrade from a pre-14.1 IP core variation that has those signals.
PTP interface signals are present in new IP core variations that you generate in the Quartus II v14.1 IP Catalog only if you turn on Enable 1588 PTP in the parameter editor. For backward compatibility, the signals remain if you upgrade from a pre-14.1 IP core variation that has those signals.
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