Advanced SEU Detection Intel® FPGA IP User Guide

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ID 683542
Date 3/26/2019
Public
Document Table of Contents
Document Table of Contents x
1. Advanced SEU Detection Intel® FPGA IP Overview 2. Advanced SEU Detection Intel® FPGA IP Functional Description 3. Using the Advanced SEU Detection Intel® FPGA IP 4. SEU Mitigation on CRAM Array 5. Advanced SEU Detection Intel® FPGA IP User Guide Archives 6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide
2. Advanced SEU Detection Intel® FPGA IP Functional Description x
2.1. On-Chip Lookup Sensitivity Processing 2.2. Off-Chip Lookup Sensitivity Processing
2.1. On-Chip Lookup Sensitivity Processing x
2.1.1. On-Chip Sensitivity Processor 2.1.2. On-Chip Processing Signals
2.2. Off-Chip Lookup Sensitivity Processing x
2.2.1. Off-Chip Lookup Sensitivity Processing Operation Flow 2.2.2. External Sensitivity Processor 2.2.3. Off-Chip Processing Signals 2.2.4. SMH Lookup
2.2.4. SMH Lookup x
2.2.4.1. SMH File Types
3. Using the Advanced SEU Detection Intel® FPGA IP x
3.1. Customizing and Generating IP Cores 3.2. Advanced SEU Detection IP Core Parameters
3.1. Customizing and Generating IP Cores x
3.1.1. IP Catalog and Parameter Editor 3.1.2. The Parameter Editor 3.1.3. Specifying IP Core Parameters and Options
3.1.3. Specifying IP Core Parameters and Options x
3.1.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
4. SEU Mitigation on CRAM Array x
4.1. Enabling the Advanced SEU Detection Feature in the Intel® Quartus® Prime Software 4.2. Hierarchy Tagging 4.3. Sensitivity Map Header File Lookup
4.2. Hierarchy Tagging x
4.2.1. Using Partitions to Specify Logic Sensitivity ID
4.3. Sensitivity Map Header File Lookup x
4.3.1. Programming Sensitivity Map Header File into Memory 4.3.2. Performing a Lookup for SMH Revision 1 ( Stratix® IV and Arria® II) 4.3.3. Performing a Lookup for SMH Revision 2 ( Stratix® V, Arria® V, and Cyclone® V Devices) 4.3.4. Performing a Lookup for SMH Revision 3 ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices)
1. Advanced SEU Detection Intel® FPGA IP Overview
2. Advanced SEU Detection Intel® FPGA IP Functional Description
3. Using the Advanced SEU Detection Intel® FPGA IP
4. SEU Mitigation on CRAM Array
5. Advanced SEU Detection Intel® FPGA IP User Guide Archives
6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide

2.2.3. Off-Chip Processing Signals

Off-chip and on-chip sensitivity processing use similar signals, except the off-chip sensitivity processing uses an EMR cache interface instead of an external memory interface.

Figure 5.  Advanced SEU Detection IP Core Signals for Off-Chip Processing
Table 3.   Advanced SEU Detection IP Core Signals for Off-Chip Processing
Interface Signals Type Width Description
Clock and Reset clk Input 1
  • Clock input.
  • Use the same input clock as the EMR Unloader IP core. The input frequency must be sufficient to process the EMR content before the next content may become available. For example, a minimum recommended frequency for Stratix V devices is 30 MHz.

    If the frequency is too low, the IP core asserts the critical_error signal if new EMR content becomes available while the IP core is processing the current content.

reset Input 1 Active-high reset.
Cache Configuration cache_comparison_off Input 1
  • Static input signal.
  • Commands the IP core to bypass cache comparison.
  • You can use this signal with the internal scrubbing feature for custom design.
Avalon-ST Sink Interface Signals3 emr Input
  • 46 (Stratix IV)
  • 67 ( Cyclone® V, Arria® V, and Stratix® V)
  • 119 ( Intel® Arria® 10 and Intel® Cyclone® 10 GX)4
EMR data input from the EMR Unloader IP core.
emr_valid Input 1 Indicates when emr data input is valid.
emr_error Input 1
  • Indicates when emr data is ignored due to an error.
  • This error may occur when there is a data overrun from the EMR Unloader IP core.
Errors critical_error Output 1 Indicates that a critical EDCRC error is detected. The IP core asserts this signal when any of the following conditions is met:
  • emr_data indicates a critical EDCRC error.
  • emr_error is asserted, indicating lost EMR content.
  • New emr_data becomes available before the previous data is processed, i.e., an emr_data overrun.
critical_clear Input 1
  • Optional input signal.
  • Assert this signal to clear the critical_error signal.
Avalon-ST Source Interface Signals cache_data Output
  • 30 (Stratix IV)
  • 35 ( Cyclone® V, Arria® V, and Stratix® V)
  • 78 ( Intel® Arria® 10 and Intel® Cyclone® 10 GX)
  • Error cache data.
  • Provides the location information for an EMR cache entry.
cache_valid Output 1 This signal is asserted when the cache contains correctable error data.
cache_ready Input 1 Indicates that the Avalon stream interface is ready.
cache_error Output 1 This Avalon stream control signal indicates a cache overflow condition. The IP core asserts this signal when new EMR data becomes available for a full cache (cache_fill_level = cache_depth).
Cache Status cache_fill_level Output 4 Indicates how many entries are in the cache.
Related Information
3 Connect the Avalon-ST streaming sink interface to the corresponding Avalon-ST source interface of the EMR Unloader IP core.
4 The actual EMR data is 78 bits only, [77:0]. Bits [118:78] are reserved.
Level Two Title