Advanced SEU Detection Intel® FPGA IP User Guide

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ID 683542
Date 3/26/2019
Public
Document Table of Contents
Document Table of Contents x
1. Advanced SEU Detection Intel® FPGA IP Overview 2. Advanced SEU Detection Intel® FPGA IP Functional Description 3. Using the Advanced SEU Detection Intel® FPGA IP 4. SEU Mitigation on CRAM Array 5. Advanced SEU Detection Intel® FPGA IP User Guide Archives 6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide
2. Advanced SEU Detection Intel® FPGA IP Functional Description x
2.1. On-Chip Lookup Sensitivity Processing 2.2. Off-Chip Lookup Sensitivity Processing
2.1. On-Chip Lookup Sensitivity Processing x
2.1.1. On-Chip Sensitivity Processor 2.1.2. On-Chip Processing Signals
2.2. Off-Chip Lookup Sensitivity Processing x
2.2.1. Off-Chip Lookup Sensitivity Processing Operation Flow 2.2.2. External Sensitivity Processor 2.2.3. Off-Chip Processing Signals 2.2.4. SMH Lookup
2.2.4. SMH Lookup x
2.2.4.1. SMH File Types
3. Using the Advanced SEU Detection Intel® FPGA IP x
3.1. Customizing and Generating IP Cores 3.2. Advanced SEU Detection IP Core Parameters
3.1. Customizing and Generating IP Cores x
3.1.1. IP Catalog and Parameter Editor 3.1.2. The Parameter Editor 3.1.3. Specifying IP Core Parameters and Options
3.1.3. Specifying IP Core Parameters and Options x
3.1.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
4. SEU Mitigation on CRAM Array x
4.1. Enabling the Advanced SEU Detection Feature in the Intel® Quartus® Prime Software 4.2. Hierarchy Tagging 4.3. Sensitivity Map Header File Lookup
4.2. Hierarchy Tagging x
4.2.1. Using Partitions to Specify Logic Sensitivity ID
4.3. Sensitivity Map Header File Lookup x
4.3.1. Programming Sensitivity Map Header File into Memory 4.3.2. Performing a Lookup for SMH Revision 1 ( Stratix® IV and Arria® II) 4.3.3. Performing a Lookup for SMH Revision 2 ( Stratix® V, Arria® V, and Cyclone® V Devices) 4.3.4. Performing a Lookup for SMH Revision 3 ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices)
1. Advanced SEU Detection Intel® FPGA IP Overview
2. Advanced SEU Detection Intel® FPGA IP Functional Description
3. Using the Advanced SEU Detection Intel® FPGA IP
4. SEU Mitigation on CRAM Array
5. Advanced SEU Detection Intel® FPGA IP User Guide Archives
6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide

6. Document Revision History for the Advanced SEU Detection Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version Changes
2019.03.26 18.1 Corrected the link to the user guide archive for version 16.0 of the Advanced SEU Detection Intel® FPGA IP.
2019.01.14 18.1

Updated the description of cache_valid in the table listing the IP core the signals for off-chip processing.

2018.09.12 18.0
  • Updated the topic about performing a lookup for SMH Revision 3 ( Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices).
  • Updated document structure.
  • Corrected a broken link to the archived user guide for the 17.1 version of the Advanced SEU Detection IP core.
2018.05.16 18.0
  • Added note to Advanced SEU Detection Core Signals for On-Chip Processing and Advanced SEU Detection Core Signals for Off-Chip Processing to indicate reserved bits in emr.
  • Renamed "Intel® FPGA Advanced SEU Detection" to "Advanced SEU Detection Intel® FPGA IP" as per Intel rebranding.
  • Added the following topics from Intel® Quartus® Prime Pro Edition Handbook:
    • On-Chip Sensitivity Processor section.
    • Off-Chip Sensitivity Processor and subtopics.
Date Version Changes
November 2017 2017.11.06
  • Rebranded as Intel.
  • Added Intel® Cyclone® 10 GX device support.
October 2016 2016.10.31
  • Added sensitivity processing as supported feature for Stratix V, Arria 10, Arria V, Arria V GZ, and Cyclone V.
  • Updated sensitivity map header information names.
May 2016 2016.05.02 Clarified the frame information array information for revision 1 .smh files.
November 2015 2015.11.02
  • Added Arria 10 support information for SMH revision 3 lookups.
  • Updated information on SMH revision 2 lookups.
  • Updated on-chip and off-chip processing signals.
  • Changed Quartus II references to Quartus Prime.
May 2015 2015.05.04
  • Added note to possible values for sensitivity_data_tag_size field.
  • Updated largest ASD region ID in the Altera Advanced SEU Detection IP Core Parameters.
  • Updated supported device for performing lookup for Revision 1 and 2.
  • Updated features and device family support by combining in a table.
  • Removed duplicated signals in Off-Chip processing signals table.
  • Updated SMH frame information array description to reduce redundancies.
June 30 2014 2014.06.30
  • Updated supported devices.
  • Replaced information about the MegaWizard Plug-in Manager with the IP Catalog.
December 2012 1.0 Initial release.
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