Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

1.13.4. Generating System Testbench Files

Platform Designer can generate testbench files that instantiate the current Platform Designer system and add Bus Functional Models (BFMs) to drive the top-level interfaces. BFMs interact with the system in the simulator.

You can generate a standard or simple testbench system with BFM or Mentor Verification IP (for AMBA* 3 AXI or AMBA* 4 AXI) components that drive the external interfaces of the system. Platform Designer generates a Verilog HDL or VHDL simulation model for the testbench system to use in the simulation tool.

First generate a testbench system, and then modify the testbench system in Platform Designer before generating the simulation model. Typically, you select only one of the simulation model options.

Follow these steps to generate system testbench files:
  1. Open and configure a system in Platform Designer.
  2. Click Generate > Generate Testbench System. The Generation dialog box appears.
  3. Specify options for the test bench system:
    Table 15.  Testbench Generation Options
    Option Description
    Create testbench Platform Designer system Specifies a simple or standard testbench system:
    • Standard, BFMs for standard Platform Designer Interconnect—Creates a testbench Platform Designer system with BFM IP components attached to exported Avalon and AMBA* 3 AXI or AMBA* 3 AXI interfaces. Includes any simulation partner modules specified by IP components in the system. The testbench generator supports AXI interfaces and can connect AMBA* 3 AXI or AMBA* 3 AXI interfaces to Mentor Graphics AMBA* 3 AXI or AMBA* 3 AXI master/slave BFMs. However, BFMs support address widths only up to 32-bits.
    • Simple, BFMs for clocks and resets—Creates a testbench Platform Designer system with BFM IP components driving only clock and reset interfaces. Includes any simulation partner modules specified by IP components in the system.
    Create testbench simulation model Specifies Verilog HDL or VHDL simulation model files and simulation scripts for the testbench. Use this option if you do not need to modify the Platform Designer-generated testbench before running the simulation.
    Output directory Specifies the path for output of generated testbench files. Turn on Clear output to remove any previously generated content from the location.
    Parallel IP Generation Turn on Use multiple processors for faster IP generation (when available) to generate IP using multiple CPUs when available in your system.
  4. Click Generate. The testbench files generate according to your specifications.
  5. Open the testbench system in Platform Designer. Make changes to the BFMs, as needed, such as changing the instance names and VHDL ID value. For example, you can modify the VHDL ID value in the Avalon Interrupt Source Intel FPGA IP component.
  6. If you modify a BFM, regenerate the simulation model for the testbench system.
  7. Compile the system and load the Platform Designer system and testbench into your simulator, and then run the simulation.