Intel® Quartus® Prime Standard Edition User Guide: Platform Designer

ID 683364
Date 12/15/2018
Public
Document Table of Contents

3.1.1.1. Fields in the Platform Designer Packet Format

The fields of the Platform Designer packet format are of variable length to minimize resource usage. However, if most components in a design have a single data width, for example 32-bits, and a single component has a data width of 64-bits, Platform Designer inserts a width adapter to accommodate 64-bit transfers.
Table 22.   Platform Designer Packet Format for Memory-Mapped Master and Slave Interfaces
Command Description
Address Specifies the byte address for the lowest byte in the current cycle. There are no restrictions on address alignment.
Size

Encodes the run-time size of the transaction.

In conjunction with address, this field describes the segment of the payload that contains valid data for a beat within the packet.

Address Sideband

Carries “address” sideband signals. The interconnect passes this field from master to slave. This field is valid for each beat in a packet, even though it is only produced and consumed by an address cycle.

Up to 8-bit sideband signals are supported for both read and write address channels.

Cache Carries the AXI cache signals.
Transaction (Exclusive) Indicates whether the transaction has exclusive access.
Transaction (Posted) Used to indicate non-posted writes (writes that require responses).
Data For command packets, carries the data to be written. For read response packets, carries the data that has been read.
Byteenable

Specifies which symbols are valid. AXI can issue or accept any byteenable pattern. For compatibility with Avalon® , Intel recommends that you use the following legal values for 32-bit data transactions between Avalon® masters and slaves:

  • 1111—Writes full 32 bits
  • 0011—Writes lower 2 bytes
  • 1100—Writes upper 2 bytes
  • 0001—Writes byte 0 only
  • 0010—Writes byte 1 only
  • 0100—Writes byte 2 only
  • 1000—Writes byte 3 only
Source_ID The ID of the master or slave that initiated the command or response.
Destination_ID The ID of the master or slave to which the command or response is directed.
Response Carries the AXI response signals.
Thread ID Carries the AXI transaction ID values.
Byte count The number of bytes remaining in the transaction, including this beat. Number of bytes requested by the packet.
Burstwrap

The burstwrap value specifies the wrapping behavior of the current burst. The burstwrap value is of the form 2<n> -1. The following types are defined:

  • Variable wrap–Variable wrap bursts can wrap at any integer power of 2 value. When the burst reaches the wrap boundary, it wraps back to the previous burst boundary so that only the low order bits are used for addressing. For example, a burst starting at address 0x1C, with a burst wrap boundary of 32 bytes and a burst size of 20 bytes, would write to addresses 0x1C, 0x0, 0x4, 0x8, and 0xC.
  • For a burst wrap boundary of size <m>, Burstwrap = <m> - 1, or for this case Burstwrap = (32 - 1) = 31 which is 25 -1.
  • For AXI masters, the burstwrap boundary value (m) is based on the different AXBURST:
    • Burstwrap set to all 1’s. For example, for a 6-bit burstwrap, burstwrap is 6'b111111.
    • For WRAP bursts, burstwrap = AXLEN * size – 1.
    • For FIXED bursts, burstwrap = size – 1.
    • Sequential bursts increment the address for each transfer in the burst. For sequential bursts, the Burstwrap field is set to all 1s. For example, with a 6-bit Burstwrap field, the value for a sequential burst is 6'b111111 or 63, which is 26 - 1.

For Avalon® masters, Platform Designer adaptation logic sets a hardwired value for the burstwrap field, according the declared master burst properties. For example, for a master that declares sequential bursting, the burstwrap field is set to ones. Similarly, masters that declare burst have their burstwrap field set to the appropriate constant value.

AXI masters choose their burst type at run-time, depending on the value of the AW or ARBURST signal. The interconnect calculates the burstwrap value at run-time for AXI masters.

Protection Access level protection. When the lowest bit is 0, the packet has normal access. When the lowest bit is 1, the packet has privileged access. For Avalon® -MM interfaces, this field maps directly to the privileged access signal, which allows a memory-mapped master to write to an on‑chip memory ROM instance. The other bits in this field support AXI secure accesses and uses the same encoding, as described in the AXI specification.
QoS

QoS (Quality of Service Signaling) is a 4-bit field that is part of the AMBA* 4 AXI interface that carries QoS information for the packet from the AXI master to the AXI slave.

Transactions from AMBA* 3 AXI and Avalon® masters have the default value 4'b0000, that indicates that they are not participating in the QoS scheme. QoS values are dropped for slaves that do not support QoS.

Data sideband Carries data sideband signals for the packet. On a write command, the data sideband directly maps to WUSER. On a read response, the data sideband directly maps to RUSER. On a write response, the data sideband directly maps to BUSER.