Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

Download PDF
ID 683240
Date 9/17/2021
Public
Document Table of Contents
Document Table of Contents x
1. About Embedded Memory IP Cores 2. Embedded Memory IP Cores Getting Started 3. Functional Description 4. Embedded Memory Design Consideration 5. Parameters and Signals 6. Design Example 7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
1. About Embedded Memory IP Cores x
1.1. Features
2. Embedded Memory IP Cores Getting Started x
2.1. Changing Parameter Settings Manually 2.2. RAM and ROM Parameter Settings
3. Functional Description x
3.1. Memory Block Types 3.2. Write and Read Operations Triggering 3.3. Port Width Configurations 3.4. Mixed-width Port Configuration 3.5. Mixed-width Ratio Configuration 3.6. Maximum Block Depth Configuration 3.7. Clocking Modes and Clock Enable 3.8. Memory Blocks Address Clock Enable Support 3.9. Byte Enable 3.10. Asynchronous Clear 3.11. Read Enable 3.12. Read-During-Write 3.13. Power-Up Conditions and Memory Initialization 3.14. Error Correction Code 3.15. Freeze Logic
3.12. Read-During-Write x
3.12.1. Selecting RDW Output Choices for Various Memory Blocks
4. Embedded Memory Design Consideration x
4.1. Avoid Providing Non-Deterministic Input
5. Parameters and Signals x
5.1. RAM: 1-Port IP Core Parameters 5.2. RAM: 2-Port IP Core Parameters 5.3. ROM: 1-PORT IP Core Parameters 5.4. ROM: 2-PORT IP Core Parameters 5.5. Signals
6. Design Example x
6.1. External ECC Implementation with True-Dual-Port RAM
6.1. External ECC Implementation with True-Dual-Port RAM x
6.1.1. Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP Core 6.1.2. Simulating the Design
6.1.2. Simulating the Design x
6.1.2.1. Simulation Results
1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

5.2. RAM: 2-Port IP Core Parameters

This table lists the parameters for the RAM: 2-Port IP core.
Table 17.  RAM: 2-Port Parameter Settings
Parameter Legal Values Description
Parameter Settings: General
How will you be using the dual port RAM?
  • With one read port and one write port
  • With two read /write ports
 Specifies how you use the dual port RAM.
How do you want to specify the memory size?
  • As a number of words
  • As a number of bits
 Determines whether to specify the memory size in words or bits.
Parameter Settings: Widths/ Blk Type
How many <X>-bit words of memory? — Specifies the number of <X>-bit words.
Use different data widths on different ports On/Off Specifies whether to use different data widths on different ports.
When you select With one read port and one write port, the following options are available:
  • How wide should the ‘q_a’ output bus be?
  • How wide should the ‘data_a’ input bus be?
  • How wide should the ‘q’ output bus be?
 — Specifies the width of the input and output ports.
When you select With two read/write ports, the following options are available:
  • How wide should the ‘q_a’ output bus be?
  • How wide should the ‘q_b’ output bus be?
What should the memory block type be? Auto, M-RAM, M4K, M512, M9K, M10K, M144K, MLAB, M20K, LCs Specifies the memory block type. The types of memory block that are available for selection depends on your target device.
How should the memory be implemented?
  • Use default logic cell style
  • Use Stratix M512 emulation logic cell style
 Specifies the logic cell implementation options. This option is enabled only when you choose LCs memory type.
Set the maximum block depth to Auto, 32, 64, 128, 256, 512, 1024, 2048, 4096 Specifies the maximum block depth in words. This option is enabled only when you set the memory block type to Auto.
Parameter Settings: Clks/Rd, Byte En
What clocking method would you like to use? When you select With one read port and one write port, the following values are available:
  • Single clock
  • Dual clock: use separate ‘input’ and ‘output’ clocks
  • Dual clock: use separate ‘read’ and ‘write’ clock
When you select With two read/write ports, the following options are available:
  • Single clock
  • Dual clock: use separate ‘input’ and ‘output’ clocks
  • Dual clock: use separate clocks for A and B ports
 Specifies the clocking method to use.
  • Single clock—A single clock and a clock enable controls all registers of the memory block.
  • Dual Clock: use separate ‘input’ and ‘output’ clocks—An input clock controls all registers related to the data input to the embedded memory block including data, address, byte enables, read enables, and write enables. An output clock controls the data output registers.
  • Dual clock: use separate ‘read’ and ‘write’ clock—A write clock controls the data-input, write-address, and write-enable registers while the read clock controls the data-output, read-address, and read-enable registers.
  • Dual clock: use separate clocks for A and B ports—Clock A controls all registers on the port A side; clock B controls all registers on the port B side. Each port also supports independent clock enables for both port A and port B registers, respectively.
When you select With one read port and one write port, the following option is available:

Create a ‘rden’ read enable signal

— Specifies whether to create a read enable signal for port B.
When you select With two read/write ports, the following option is available:

Create a ‘rden_a’ and ‘rden_b’ read enable signal

Specifies whether to create a read enable signal for port A and B.
Create byte enable for port A — Specifies whether to create a byte enable for port A and B. Turn on these options if you want to mask the input data so that only specific bytes, nibbles, or bits of data are written.

To enable byte enable for port A and port B, the data width ratio has to be 1 or 2 for the RAM: 1-PORT and RAM: 2-PORT IP cores.

The option to create a byte enable for port B is only available when you select the With two read/write ports option.
Create byte enable for port B —
Enable error checking and correcting (ECC) to check and correct single bit errors and detect double errors On/Off Specifies whether to enable the ECC feature that corrects single bit errors and detects double errors at the output of the memory. This option is only available in devices that support M144K memory block type.
Enable error checking and correcting (ECC) to check and correct single bit errors, double adjacent bit errors, and detect triple adjacent bit errors On/Off Specifies whether to enable the ECC feature that corrects single bit errors, double adjacent bit errors, and detects triple adjacent bit errors at the output of the memory. This option is only available in devices that support M20K memory block type.
Parameter Settings: Regs/Clkens/Aclrs
Which ports should be registered?

When you select With one read port and one write port, the following options are available:

  • ‘data’, ‘wraddress’, and ‘wren’ write input ports
  • ‘raddress’ and ‘rden’ read input port
  • Read output port(s) ‘q’

When you select With two read/write ports, the following options are available:

  • ‘data_a’, ‘wraddress_a’, and ‘wren_a’ write input ports
  • Read output port(s) ‘q’_a and ‘q_b’
 On/Off Specifies whether to register the read or write input and output ports.
More Options

When you select With one read port and one write port, the following options are available:

  • ‘data’ port
  • ‘wraddress’ port
  • ‘wren’ port
  • ‘raddress’ port
  • ‘q_b’ port

When you select With two read /write ports, the following options are available:

  • ‘data_a’ port
  • ‘data_b’ port
  • ‘wraddress_a’ port
  • ‘wraddress_b’ port
  • ‘wren_a’ port
  • ‘wren_b’ port
  • ‘q_a’ port
  • ‘q_b’ port
 On/Off The read and write input ports are turned on by default. You only need to specify whether to register the Q output ports.
Create one clock enable signal for each clock signal. On/Off Specifies whether to turn on the option to create one clock enable signal for each clock signal.
More Options

When you select With one read port and one write port, the following option is available:

  • Use clock enable for write input registers

When you select With two read /write ports, the following options are available:

  • Use clock enable for port A input registers
  • Use clock enable for port B input registers
  • Use clock enable for port A output registers
  • Use clock enable for port B output register
 On/Off Clock enable for port B input and output registers are turned on by default. You only need to specify whether to use clock enable for port A input and output registers.
More Options

When you select With one read port and one write port, the following options are available:

  • Create an ‘wr_addressstall’ input port.
  • Create an ‘rd_addressstall’ input port.

When you select With two read /write ports, the following options are available:

  • Create an ‘addressstall_a’ input port.
  • Create an ‘addressstall_b’ input port.
 On/Off Specifies whether to create clock enables for address registers. You can create these ports to act as an extra active low clock enable input for the address registers.
Create an ‘aclr’ asynchronous clear for the registered ports. On/Off Specifies whether to create an asynchronous clear port for the registered ports.
More Options

When you select With one read port and one write port, the following options are available:

  • ‘q_b’ port
  • ‘rdaddress’ port

When you select With two read /write ports, the following options are available:

  • ‘q_a’ port
  • ‘q_b’ port
 On/Off Specifies whether the ‘raddress’, ‘q_a’, and ‘q_b’ ports are cleared by the aclr port.
Parameter Settings: Output 1

When you select With one read port and one write port, the following option is available:

  • How should the q output behave when reading a memory location that is being written from the other port?

When you select With two read /write ports, the following option is available:

  • How should the q_a and q_b outputs behave when reading a memory location that is being written from the other port?
  • Old memory contents appear
  • I do not care

Specifies the output behavior when read-during-write occurs.

  • Old memory contents appear— The RAM outputs reflect the old data at that address before the write operation proceeds.
  • I do not care—This option functions differently when you turn it on depending on the following memory block type you select:
    • When you set the memory block type to Auto, M144K, M512, M4K, M9K, M10K, M20K or any other block RAM, the RAM outputs ‘don't care’ or “unknown” values for read-during-write operation without analyzing the timing path.
    • When you set the memory block type to MLAB (for LUTRAM), the RAM outputs ‘dont care’ or ‘unknown’ values for read-during-write operation but analyzes the timing path to prevent metastability.
Do not analyze the timing between write and read operation. Metastability issues are prevented by never writing and reading at the same address at the same time. On/Off Turn on this option when you want the RAM to output ‘don’t care’ or unknown values for read-during-write operation without analyzing the timing path. This option is only available for LUTRAM and is enabled when you set memory block type to MLAB.
Parameter Settings: Output 2 (This tab is only available when you select two read/ write ports)
What should the ‘q_a’ output be when reading from a memory location being written to?
  • New data
  • Old Data

Specifies the output behavior when read-during-write occurs.

  • New Data—New data is available on the rising edge of the same clock cycle on which it was written.
  • Old Data—The RAM outputs reflect the old data at that address before the write operation proceeds.
What should the ‘q_b’ output be when reading from a memory location being written to?
Get x’s for write masked bytes instead of old data when byte enable is used On/Off Turn on this option to obtain ‘X’ on the masked byte.
Parameter Settings: Mem Init
Do you want to specify the initial content of the memory?
  • No, leave it blank
  • Yes, use this file for the memory content data

Specifies the initial content of the memory.

To initialize the memory to zero, select No, leave it blank.

To use a memory initialization file (.mif) or a hexadecimal (Intel-format) file (.hex), select Yes, use this file for the memory content data.

Enable Partial Reconfiguration Initialization Mode On/Off Initializes a clock enable circuit in the same PR region as the RAM.
Implement clock-enable circuitry for use in a partial reconfiguration region On/Off Specifies whether to implement clock-enable circuitry for use in a partial reconfiguration region.
Level Two Title