Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

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ID 683240
Date 9/17/2021
Public
Document Table of Contents
Document Table of Contents x
1. About Embedded Memory IP Cores 2. Embedded Memory IP Cores Getting Started 3. Functional Description 4. Embedded Memory Design Consideration 5. Parameters and Signals 6. Design Example 7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide
1. About Embedded Memory IP Cores x
1.1. Features
2. Embedded Memory IP Cores Getting Started x
2.1. Changing Parameter Settings Manually 2.2. RAM and ROM Parameter Settings
3. Functional Description x
3.1. Memory Block Types 3.2. Write and Read Operations Triggering 3.3. Port Width Configurations 3.4. Mixed-width Port Configuration 3.5. Mixed-width Ratio Configuration 3.6. Maximum Block Depth Configuration 3.7. Clocking Modes and Clock Enable 3.8. Memory Blocks Address Clock Enable Support 3.9. Byte Enable 3.10. Asynchronous Clear 3.11. Read Enable 3.12. Read-During-Write 3.13. Power-Up Conditions and Memory Initialization 3.14. Error Correction Code 3.15. Freeze Logic
3.12. Read-During-Write x
3.12.1. Selecting RDW Output Choices for Various Memory Blocks
4. Embedded Memory Design Consideration x
4.1. Avoid Providing Non-Deterministic Input
5. Parameters and Signals x
5.1. RAM: 1-Port IP Core Parameters 5.2. RAM: 2-Port IP Core Parameters 5.3. ROM: 1-PORT IP Core Parameters 5.4. ROM: 2-PORT IP Core Parameters 5.5. Signals
6. Design Example x
6.1. External ECC Implementation with True-Dual-Port RAM
6.1. External ECC Implementation with True-Dual-Port RAM x
6.1.1. Generating the ALTECC_ENCODER and ALTECC_DECODER with the RAM: 2-PORT IP Core 6.1.2. Simulating the Design
6.1.2. Simulating the Design x
6.1.2.1. Simulation Results
1. About Embedded Memory IP Cores
2. Embedded Memory IP Cores Getting Started
3. Functional Description
4. Embedded Memory Design Consideration
5. Parameters and Signals
6. Design Example
7. Document Revision History for the Embedded Memory (RAM: 1-PORT, RAM: 2-PORT, ROM: 1-PORT, and ROM: 2-PORT) User Guide

3.14. Error Correction Code

The error correction code (ECC) feature detects and corrects output data errors. You have the option to use pipeline registers to improve performance. The ECC feature is supported only in the following conditions:

  • Memory blocks and not MLABs or logic cells
  • Simple dual-port mode
  • Same-width ports
  • Byte-enable feature is disabled
Note: When the ECC feature is enabled, the result of a RDW in a mixed-port configuration is always Don't care.
Note: The simulation model does not support the ECC feature for Intel® Arria® 10 devices.
Table 14.  ECC Features in Memory Blocks
Memory Block Supported Port Width Single Error Double Adjacent Error Triple Adjacent Error
M144K Up to 64 bits Detection and correction Detection only –
M20K Up to 32 bits Detection and correction Detection and correction Detection only
M20K ( Intel® Arria® 10) More than 32 bits—achieved by stitching 32-bit M20K blocks together.
Table 15.  Error StatusThe IP uses the eccstatus signal to indicate the status of the error detection and correction.
M144K

eccstatus[2..0]

 M20K

eccstatus[1..0]

 Description
000 00 No error.
011 – Single error was detected and corrected.
101 – Double error was detected.
001 01 Illegal status.
010 01 Illegal status.
100 01 Illegal status.
11X 01 Illegal status.
– 10 An error was detected and corrected. However, the memory array is not updated.
– 11 An error was detected but not corrected in the output data.
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