AN 798: Partial Reconfiguration with the Arria 10 HPS

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ID 683034
Date 1/25/2017
Public
Document Table of Contents
Document Table of Contents x
Partial Reconfiguration with the Intel® Arria® 10 HPS
Partial Reconfiguration with the Intel® Arria® 10 HPS x
Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Prerequisites for Using This Document x
Knowledge Prerequisites Software Tool Prerequisites Hardware Prerequisites
Partial Reconfiguration Tools and Methods x
Hardware Tools and Methods Software Tools and Methods
Hardware Tools and Methods x
Arria 10 SoC Partial Reconfiguration Support Overview of the Arria 10 GHRD
Arria 10 SoC Partial Reconfiguration Workflow x
Hardware Workflow Software Workflow
Creating the PR Example Design x
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
Qsys Partial Reconfiguration Freeze Logic x
PR Freeze Bridge PR Freeze Controller
Add a Partial Reconfiguration Region to the GHRD x
Creating the Partial Reconfiguration Design Adding the PR Region Connecting New Ports in the GHRD Module Instantiation
Generating the Example Software Image x
Overview of Software Image Creation Generating a New Boot Device Tree Creating the Device Tree Overlays
Generating a New Boot Device Tree x
Critical Information in the Default Device Tree Steps to Create a New Device Tree
Loading Partial Reconfiguration Designs Using Linux x
Installing Files on the SD Card Loading and Unloading the Device Tree Overlays
Partial Reconfiguration with the Intel® Arria® 10 HPS

Adding the PR Region

  1. Reopen the GHRD Qsys system design.
  2. Add an Intel® partial reconfiguration freeze controller.
    Figure 14. Adding the Partial Reconfiguration Freeze Controller
  3. Add an Intel partial reconfiguration freeze bridge.
    Figure 15. Adding the Partial Reconfiguration Freeze Bridge
  4. Add the PR Region Default Qsys system to the design as shown below. The previously created pr_region_default Qsys system is in the System category of the IP catalog.
    Figure 16. Adding the PR Region Default Qsys System
  5. Confirm the additions to the GHRD Qsys system design by comparing the System Contents tab shown below.
    Figure 17. Resulting Design
  6. Connect the new components as shown below. Export the pr_handshake conduit interface of the Intel® partial reconfiguration freeze controller to the top level with the name pr_handshake.
    Note: The freeze controller's interrupt_sender output signal is disconnected, because the Linux driver polls a status bit rather than using an interrupt. You might see a Qsys warning message, which you can ignore.
    Figure 18. PR Region Connections
  7. Edit the system address memory map using the Address Map tab as shown below.
    Note: Pay attention to the freeze controller and freeze bridge base addresses. These are crucial parts of the handoff information provided to the host software designer.
    Figure 19. System Address Memory Map
  8. Force the pb_lwh2f address width to automatically readjust by unchecking, and then re-checking the Use automatically-determined address width box in the component dialog. Qsys sets the address width to 12 bits.
    Figure 20. Pipeline Bridge Data Width
  9. Adjust the address map to eliminate any overlaps or alignment issues.
  10. Click Generate RTL to create the new system.
  11. Click Finish.
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